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參數(shù)資料
| 型號(hào)： | AD9755ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 300MSPS 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 165mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 300M |
| 配用： | AD9755-EB-ND - BOARD EVAL FOR AD9755 |
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REV. B
AD9755
–10–
AD9755
IOUTA
IOUTB
SEGMENTED
SWITCHES FOR
DB0 TO DB13
DAC
FSADJ
REFIO
1.2V REF
DIV0
PLLLOCK
DIGITAL DATA INPUTS
0.1 F
RSET
2k
RLOAD
50
DB0 – DB13
DCOM
PMOS CURRENT
SOURCE ARRAY
AVDD
3.0V TO 3.6V
DVDD
2–1 MUX
PORT 1 LATCH
DAC LATCH
ACOM
DIV1
PLL
CIRCUITRY
PLLVDD
CLKVDD
CLK+
CLK–
CLKCOM
RESET
LPF
DB0 – DB13
VOUTB
RLOAD
50
VOUTA
VDIFF = VOUTA – VOUTB
PORT 2 LATCH
Figure 3. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9755. The
AD9755 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, IOUTFS. The array is
divided into 31 equal sources that make up the five most significant
bits (MSBs). The next four bits, or middle bits, consist of 15 equal
current sources whose value is 1/16th of an MSB current source.
The remaining LSBs are a binary weighted fraction of the middle
bit current sources. Implementing the middle and lower bits
with current sources, instead of an R-2R ladder, enhances dynamic
performance for multitone or low amplitude signals and helps
maintain the DAC’s high output impedance (i.e., >100 k
).
All of the current sources are switched to one or the other of the
two outputs (i.e., IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on a new architecture that
significantly improves distortion performance. This new switch
architecture reduces various timing errors and provides matching
complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9755 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V band gap voltage
reference, and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET. The external resistor, in combination
with both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is 32 times the value of IREF.
REFERENCE OPERATION
The AD9755 contains an internal 1.20 V band gap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an input or output,
depending on whether the internal or an external reference is used.
To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1
F capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is
to be used elsewhere in the circuit, an external buffer amplifier
with an input bias current less than 100 nA should be used. An
example of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO, as
shown in Figure 5. The external reference may provide either a
fixed reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. Note that the 0.1
F
compensation capacitor is not required since the internal reference
is overdriven, and the relatively high input impedance of REFIO
minimizes any loading of the external reference.
REFERENCE CONTROL AMPLIFIER
The AD9755 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a voltage-to-current con-
verter as shown in Figure 4, so that its current output, IREF, is
determined by the ratio of VREFIO and an external resistor, RSET,
as stated in Equation 4. IREF is applied to the segmented current
sources with the proper scaling factor to set IOUTFS, as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5
A and 625 A. The wide adjustment span of I
OUTFS provides
several application benefits. The first benefit relates directly to
the power dissipation of the AD9755, which is proportional to
IOUTFS (refer to the Power Dissipation section). The second
benefit relates to the 20 dB adjustment, which is useful for sys-
tem gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency, small
signal multiplying applications.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9755-EB | 功能描述:BOARD EVAL FOR AD9755 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD976 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| AD9760 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 125 MSPS TxDAC D/A Converter |
| AD9760-50AR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
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