參數(shù)資料
型號： AD9742ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/32頁
文件大小： 0K
描述： IC DAC 12BIT 210MSPS 32LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
設(shè)置時(shí)間： 11ns
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 145mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 210M
配用： AD9742ACP-PCBZ-ND - BOARD EVAL FOR AD9742ACP
Data Sheet
AD9742
Rev. C | Page 15 of 32
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. The AD9742 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when applying
the AD9742 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 27 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement,
while at higher rates, more care must be taken.
–3
–2
2
–1
0
1
65
75
ns
dB
3
55
45
35
60
70
50
40
50MHz SFDR
20MHz SFDR
50MHz SFDR
02912-B-026
Figure 27. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a Logic Level 1
to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5
AVDD. This digital input also contains an active pull-down circuit
that ensures that the AD9742 remains enabled if this input is
left disconnected. The AD9742 takes less than 50 ns to power
down and approximately 5 s to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on several
factors that include:
The power supply voltages (AVDD, CLKVDD, and DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly
proportional to IOUTFS, as shown in Figure 28, and is insensitive to
fCLOCK. Conversely, IDVDD is dependent on both the digital input
waveform, fCLOCK, and digital supply DVDD. Figure 29 shows
IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
IOUTFS (mA)
35
0
2
I AVDD
(mA)
30
25
20
15
10
4
6
8
10
12
14
16
18
20
02912-B-027
Figure 28. IAVDD vs. IOUTFS
RATIO (fOUT/fCLOCK)
20
0.01
1
0.1
I DVDD
(mA)
18
16
14
12
10
8
6
4
2
0
165MSPS
125MSPS
65MSPS
02912-B-028
210MSPS
Figure 29. IDVDD vs. Ratio @ DVDD = 3.3 V
0
50
250
100
150
200
0
2
4
6
8
12
10
fCLOCK (MSPS)
I
CLKVDD
(mA)
DIFF
PECL
SE
02912-B-029
Figure 30. ICLKVDD vs. fCLOCK and Clock Mode
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