參數(shù)資料
型號： AD9742ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/32頁
文件大?。?/td> 0K
描述： IC DAC 12BIT 210MSPS 32LFCSP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1
系列： TxDAC®
設(shè)置時間： 11ns
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 145mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 210M
配用： AD9742ACP-PCBZ-ND - BOARD EVAL FOR AD9742ACP
AD9742
Data Sheet
Rev. C | Page 12 of 32
FUNCTIONAL DESCRIPTION
AD9742 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (IOUTFS). The array is divided into 31 equal currents that
make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16th of an MSB current source. The remaining LSBs
are binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance (i.e., >100 k).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further
refinements to reduce distortion contributed by the switching
transient. This switch architecture also reduces various timing
errors and provides matching complementary drive signals to
the inputs of the differential current switches.
The analog and digital sections of the AD9742 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 210 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET, connected to the full-scale adjust (FS
ADJ) pin. The external resistor, in combination with both the
reference control amplifier and voltage reference ,VREFIO, sets the
reference current, IREF, which is replicated to the segmented
current sources with the proper scaling factor. The full-scale
current, IOUTFS, is 32 times IREF.
REFERENCE OPERATION
The AD9742 contains an internal 1.2 V band gap reference. The
internal reference can be disabled by raising REFLO to AVDD.
It can also be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or an
output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 F capacitor and connect
REFLO to ACOM via a resistance less than 5 . The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is shown in Figure 23.
150pF
1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
2k
0.1
F
AD9742
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
02912-B-022
Figure 23. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
Figure 24. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 F
compensation capacitor is not required since the internal
reference is overridden, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
150pF
1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
REFIO
FS ADJ
RSET
AD9742
EXTERNAL
REF
IREF =
VREFIO/RSET
AVDD
REFERENCE
CONTROL
AMPLIFIER
VREFIO
3.3V
02912-B-023
Figure 24. External Reference Configuration
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