
AD9720/AD9721
–6–
REV. A
T he REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. T he analog signal for this
mode of operation must have a signal swing in the range of
–3.3 V to –4.25 V. T his can be implemented by capacitively
coupling into REFERENCE IN a signal with a dc bias of –3.3 V
(I
OUT
~ 22.5 mA) to –4.25 V (I
OUT
~ 3 mA), as shown in Figure
2, or by driving REFERENCE IN with a low impedance op
amp whose signal swing is limited to the stated range.
—
–V
S
23
REFERENCE
IN
AD9720/AD9721
–V
S
–3.8V
Figure 2. Wideband Multiplying Circuit
Outputs
T he Switch Network provides complementary current outputs
I
OUT
and
I
OUT
. T he design of the AD9720/AD9721 is based on
statistical current source matching which provides 10-bit linear-
ity without trim. Current is steered to either I
OUT
or
I
OUT
in
proportion to the digital input code. T he sum of the two cur-
rents is always equal to the full-scale output current minus one
LSB.
T he current output can be converted to a voltage by resistive
loading as shown in the block diagram. Both I
OUT
and
I
OUT
should be loaded equally for best overall performance. T he volt-
age which is developed is the product of the output current and
the value of the load resistor.
An operational amplifier can also be used to perform the I to V
conversion of the DAC output. Figure 3 shows an example of a
circuit which uses the AD9617, a high speed, current feedback
amplifier. T he resistor values in Figure 3 provide a 4.096 V
swing, centered at ground, at the output of the AD9617
amplifier.
±
2.048 V
AD9617
–
+
R
FF
20
AD9720/
AD9721
I
OS
R
L
I
FS
V
OUT
R
FB
25
25
26
R2
100
–
+
1/2
AD708
R1
10k
10k
200
25
REF
OUT
CONTROL
AMP IN
400
21
I
OUT
I
–
+
1/2
AD708
Figure 3. I/V Conversion Using Current Feedback Amp
DDS Applications
T he performance characteristics of the AD9720/AD9721 make
it ideally suited for direct digital synthesis (DDS) and other
waveform generation applications. Since the aliased distortion of
the DAC collects around the fundamental when generating fre-
quencies which are nearly integer fractions of the clock rate,
these are often considered worst case conditions.
Please contact the factory for information concerning the avail-
ability of an evaluation board or for additional characterization
data.
5 ns/DIVISION
2
SETTLING TIME
≈
4.5ns
NET GLITCH = 1.34pV-s
PEAK GLITCH = 1.36pV-s
I
OUT
AD9720
50
TEST CIRCUIT
100 MHz
LPF
Figure 4. AD9720 Glitch Impulse