
AAD9720/AD9721
–3–
REV. A
NOT ES
1
Measured as error in ratio of full-scale current to current through R
(640
μ
A nominal); ratio is nominally 32. DAC load is virtual ground.
1
2
Full-scale current variations among devices are higher when driving REFERENCE IN directly.
1
3
Frequency at which a 3 dB change in output of DAC is observed, R
= 50
; 100 mV modulation at midscale.
1
4
Based on I
= 32 (CONT ROL AMP IN/R
) when using internal control amplifier. DAC load is virtual ground.
1
5
Measured as voltage settling at midscale transition to
±
0.1%; R
= 50
.
1
6
Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
1
7
Peak glitch impulse is measured as the largest area under a single positive or negative transient.
1
8
Measured with R
= 50
and DAC operating in latched mode.
1
9
Data must remain stable for specified time prior to rising edge of CLOCK .
10
Data must remain stable for specified time after rising edge of CLOCK .
11
SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at
the fundamental frequency and covers the indicated span.
12
Supply voltages should remain stable within
±
5% for normal operation.
13
190 mA typ on Digital –V
, 30 mA typ on Analog –V
.
14
Measured at
±
5% of +V
S
(AD9721 only) and –V
S
(AD9720 or AD9721) using external reference.
Specifications subject to change without notice.
ABSOLUT E MAX IMUM RAT INGS
1
Positive Supply Voltage (+V
S
) (AD9721 Only) . . . . . . . . +6 V
Negative Supply Voltage (–V
S
)
(AD9720 and AD9721) . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Digital Input Voltages (D
1
–D
10
, CLOCK ,
CLOCK
)
AD9720 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to –V
S
AD9721 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V
S
Internal Reference Output Current . . . . . . . . . . . . . . . 500
μ
A
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V
Control Amplifier Output Current . . . . . . . . . . . . . .
±
2.5 mA
Reference Input Voltage Range (V
REF
) . . . . . . . . . .0 V to –V
S
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating T emperature Range
AD9720/AD9721BN/BR . . . . . . . . . . . . . . –25
°
C to +85
°
C
AD9720/AD9721T E/T Q . . . . . . . . . . . . . –55
°
C to +125
°
C
Maximum Junction T emperature
2
AD9720/AD9721BN/BR . . . . . . . . . . . . . . . . . . . . .+150
°
C
AD9720/AD9721T E/T Q . . . . . . . . . . . . . . . . . . . . .+175
°
C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . .+300
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
NOT ES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
T ypical thermal impedances:
28-Lead plastic DIP:
θ
JA
= 37
°
C/W,
θ
JC
= 10
°
C/W;
28-Leadless LCC:
θ
JA
= 41
°
C/W,
θ
JC
= 13
°
C/W;
28-Lead SOIC:
θ
JA
= 46
°
C/W,
θ
JC
= 10
°
C/W;
28-Lead Cerdip:
θ
JA
= 35
°
C/W,
θ
JC
= 10
°
C/W.
Soldered to board; no air flow.
E X PLANAT ION OF T E ST LE VE LS
T est Level
I
– 100% production tested.
II – 100% production tested at +25
°
C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V
– Parameter is a typical value only.
VI – All devices are 100% tested at +25
°
C. 100% production
tested at temperature extremes for extended temperature
devices; sample tested at temperature extremes for com-
mercial/industrial devices.
DIE LAY OUT AND ME CHANICAL INFORMAT ION
Die Dimensions . . . . . . . . . . . . . . . 199
3
165
3
15 (
±
2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3
4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
ORDE RING GUIDE
T emperature
Range
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
–25
°
C to +85
°
C
–25
°
C to +85
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
Package
Description
28-Lead Plastic DIP
28-Lead SOIC
28-Leadless LCC
28-Lead Cerdip
Package
Options
N-28
R-28
E-28A
Q-28
Model
AD9720BN
AD9720BR
AD9720T E
AD9720T Q
AD9721BN
AD9721BR
AD9721T E
AD9721T Q
28-Lead Plastic DIP
28-Lead SOIC
28-Leadless LCC
28-Lead Cerdip
N-28
R-28
E-28A
Q-28