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參數(shù)資料
| 型號： | AD9720 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 400 MSPS D/A Converters(400MSPS10位D/A轉(zhuǎn)換器) |
| 中文描述： | 10位，400 MSPS的D / A轉(zhuǎn)換（400MSPS10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 188K |
| 代理商： | AD9720 |
AD9720/AD9721
–5–
REV. A
t
S
t
H
t
PD
OUTPUT
CLOCK
t
S
– INPUT SETUP TIME
t
H
– INPUT HOLD TIME
– OUTPUT PROPAGATION DELAY
t
PD
t
ST
– OUTPUT SETTLING TIME
OUTPUT
ERROR
ERROR
BAND
t
PD
t
ST
CLOCK
CODE 2
VALID DATA
CODE 1
VALID DATA
DATA INPUTS
D – D
10
CODE 1
CODE 2
CLOCK
CLOCK
AD9720/AD9721 Timing Diagram
T HE ORY AND APPLICAT IONS
T he AD9720/AD9721 high speed digital-to-analog converters
utilize Most Significant Bit (MSB) decoding and segmentation
techniques to reduce glitch impulse and maintain 10-bit linear-
ity without trimming.
As shown in the functional block diagram, the design is based
on four main subsections: the Decoder/Driver circuits, the Edge
T riggered Data Register, the Switch Network, and the Control
Amplifier. An internal bandgap reference is also included to al-
low operation with a minimum of external components. T he
block labeled “Inverters” is transparent in normal operation, but
can be used to minimize the external components requirements
in DDS applications using the AD9950, a 300 MSPS phase ac-
cumulator (see AD9950 data sheet).
Digital Inputs/T iming
T he AD9720 employs single-ended ECL-compatible inputs for
data inputs D
1
–D
10
and the differential clock signals CLOCK
and
CLOCK
. T he internal ECL midpoint reference is designed
to match 10K ECL device thresholds. On the AD9721, a T T L
translator is added at each input and the clock becomes single
ended; with these exceptions, the AD9720 and AD9721 are
identical. (NOT E: Pin 14 is +V
S
on AD9721; –V
S
on AD9720.)
In the Decoder/Driver section, the four MSBs (D
1
–D
4
) are de-
coded to 15 “thermometer code” lines. An equalizing delay is
included for the six Least Significant Bits (LSBs) and the clock
signals. T his delay minimizes data skew and data setup and hold
times at the register inputs.
T he onboard register is rising-edge-triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data set-up and hold times as shown in the
timing diagram.
Although the AD9720/AD9721 chip is designed to provide iso-
lation from digital inputs to the outputs, some coupling of digi-
tal transitions is inevitable, especially with T T L or CMOS
inputs applied to the AD9721. Digital feedthrough can be re-
duced by forming a low-pass filter using a resistor in series with
the capacitance of each digital input; this rolls off the slew rate
of the digital inputs.
References
As shown in the functional block diagram, the internal band-gap
reference, control amplifier, and reference input are pinned out
for maximum user flexibility when setting the reference.
When using the internal reference, REFERENCE OUT (Pin
25) should be connected to CONT ROL AMP IN (Pin 26).
CONT ROL AMP OUT (Pin 24) should be connected to REF-
ERENCE IN (Pin 23). A 0.1
μ
F ceramic capacitor from Pin 23
to ANALOG –V
S
(Pin 22) improves settling by decoupling
switching noise from the current sink base line. A reference
current cell provides feedback to the control amp by sinking
current through R
SET
(Pin 17).
Full-scale output current is determined by CONT ROL AMP IN
and R
SET
according to the equation:
I
OUT
(
FS
) = (
CONTROL AMP IN/R
SET
)
3
32
T he internal reference is nominally –1.25 V with a tolerance of
±
8% and typical drift over temperature of 100 ppm/
°
C. If
greater accuracy or better temperature stability is required, an
external reference can be utilized. T he AD589 reference features
±
10 ppm/
°
C drift over temperatures from 0
°
C to +70
°
C.
T wo modes of multiplying operation are possible with the
AD9720/AD9721. Signals with bandwidths up to 1 MHz and
input swings from –0.6 V to –1.2 V can be applied to the CON-
T ROL AMP input as shown in Figure 1. Because the control
amplifier is internally compensated, the 0.1
μ
F capacitor dis-
cussed above can be reduced to maximize the multiplying band-
width. However, it should be noted that settling time for
changes to the digital inputs will be degraded.
–0.6V TO –1.2V
400 kHz MAX
R
SET
CONTROL
AMP IN
26
CONTROL
AMP OUT
REFERENCE
IN
17
AD9720/AD9721
24
23
ANALOG – V
S
0.1μF
R
SET
R
T
Figure 1. Low Frequency Multiplying Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9721 | 10-Bit, 400 MSPS D/A Converters(400MSPS10位D/A轉(zhuǎn)換器) |
| AD9725 | 14-Bit, 600+ MSPS D/A Converter |
| AD9725BSV | 14-Bit, 600+ MSPS D/A Converter |
| AD9731BR | 10-Bit, 170 MSPS D/A Converter |
| AD9731BRS | 10-Bit, 170 MSPS D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9720BN | 制造商:Rochester Electronics LLC 功能描述:10BIT 400MSPS DAC IC IC - Bulk |
| AD9720BR | 制造商:Analog Devices 功能描述:PARALLEL, WORD INPUT LOADING, 0.0045 us SETTLING TIME, 10-BIT DAC, PDSO28 |
| AD9720TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
| ad9720te/883b | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9720TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
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