
AD9720/AD9721
–4–
REV. A
DIP & SOIC Packages
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9720/
AD9721
D
1
(MSB)
REFERENCE OUT
CONTROL AMP IN
DIGITAL –V
S
GROUND
D
2
D
3
D
4
D
5
D
6
D
7
ANALOG –V
S
I
OUT
REFERENCE IN
CONTROL AMP OUT
D
8
D
9
D
10
(LSB)
ANALOG RETURN
I
OUT
CLOCK
(NC)
INVERT
DIGITAL –V
S
(+V
S
)
GROUND
GROUND
DIGITAL –V
S
R
SET
DIP
LCC Package
28
27
1
2
3
4
26
25
21
22
23
24
19
20
TOP VIEW
(Not to Scale)
5
6
7
8
9
10
11
12 13
14
D
S
D
S
)
15
G
16
D
S
17
R
S
18
G
AD9720/AD9721
LCC
REFERENCE OUT
CONTROL AMP OUT
REFERENCE IN
ANALOG –V
S
I
OUT
I
OUT
ANALOG RETURN
D
5
D
6
D
7
D
8
D
9
D
10
(LSB)
CLOCK
G
D
S
A
D
2
D
1
I
D
4
D
PIN CONFIGURAT IONS
PIN FUNCT ION DE SCRIPT IONS
DIP
Pin # Name
Function
1
2–9
D
1
(MSB)
D
2
–D
9
Most Significant Bit (MSB) of digital input word.
Eight of 10 digital input bits. Digital inputs are 10K ECL compatible for AD9720; T T L compatible
for AD9721. See coding table elsewhere.
Least Significant Bit (LSB) of digital input word.
10
D
10
(LSB)
Input Coding vs. Current Output
Input Code D
1
–D
10
1111111111
0000000000
I
OUT
(mA)
–20.48
0
I
OUT
(mA)
0
–20.48
11
CLOCK
Edge-triggered latch enable signal for on-board registers. 10K ECL compatible for AD9720. T T L
compatible for AD9721. Register loads data on rising edge of CLOCK signal; must be driven in con-
junction with CLOCK .
Complementary edge-triggered latch enable signal for on-board registers. 10K ECL compatible for
AD9720; not connected (NC) for AD9721.
Normally connected to logic LOW; inverters are transparent in this mode. Logic High inverts the 9
LSBs (D
2
–D
10
) when the MSB is LOW. No internal pull-down resistor.
One of three digital supply pins; nominally –5.2 V for AD9720; +5 V for AD9721.
Converter ground return.
One of three negative digital supply pins; nominally –5.2 V.
Connection for external resistance reference; nominally 1,960
. Full-scale current out = 32
3
(CONT ROL AMP IN/R
SET
) when using internal amplifier. DAC load is virtual ground.
Converter ground return.
Analog current return. T his point and the reference side of the DAC load resistors should be con-
nected to the same potential (nominally ground).
Analog current output; full-scale output occurs with digital inputs at all “1.” With external load resis-
tor, output voltage I
OUT
3
(R
LOAD
i
R
INT ERNAL
). R
INT ERNAL
is nominally 210
.
Complementary analog current output; zero-scale output occurs with digital inputs at all “1.”
Negative analog supply; nominally –5.2 V.
Normally connected to CONT ROL AMP OUT (Pin 24). Direct line to DAC current source network.
Voltage changes (noise) at this point have a direct effect on the full-scale output current of DAC.
Full-scale current output = 32
3
(CONT ROL AMP IN/R
SET
) when using internal amplifier. DAC
load is virtual ground.
Normally connected to REFERENCE INPUT (Pin 23). Output of internal control amplifier, which
provides a reference for the current switch network.
Normally connected to CONT ROL AMP IN (Pin 26). Internal voltage reference, nominally –1.25 V.
Normally connected to REFERENCE OUT (Pin 25) if not connected to external reference.
One of three negative digital supply pins; nominally –5.2 V.
Converter ground return.
12
CLOCK
/NC
13
INVERT
14
15
16
17
DIGIT AL –V
S
/+V
S
GROUND
DIGIT AL –V
S
R
SET
18
19
GROUND
ANALOG RET URN
20
I
OUT
21
22
23
I
OUT
ANALOG –V
S
REFERENCE IN
24
CONT ROL AMP OUT
25
26
27
28
REFERENCE OUT
CONT ROL AMP IN
DIGIT AL –V
S
GROUND