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參數(shù)資料
| 型號： | AD9643BCPZ-210 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大小： | 1659K |
| 代理商： | AD9643BCPZ-210 |
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AD9643
Rev. A | Page 26 of 36
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9643 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9643.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time period that
the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
SNRHF = 10 log[(2π × fIN × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
80
75
70
65
60
55
50
1
10
100
1000
INPUT FREQUENCY (MHz)
S
NR
(
d
Bc)
09
636
-0
60
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
Figure 56. AD9643-250 SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9643.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter, for
more information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the power dissipated by the AD9643 is
proportional to its sample rate. The data in Figure 57 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0
40
60
80
100
120
140
160
180
200
220
240
ENCODE FREQUENCY (MSPS)
TO
TA
L
P
O
W
E
R
(W
)
S
U
P
L
Y
CURRE
NT
(A)
09
636
-0
61
TOTAL POWER
IAVDD
IDRVDD
Figure 57. AD9643-250 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9643 is placed in power-down
mode. In this state, the ADC typically dissipates 10 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD9643 to its
normal operating mode. Note that PDWN is referenced to the
digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI, for additional details.
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