參數(shù)資料
型號(hào): AD9640ABCPZ-125
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 49/52頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 125MSPS 64LFCSP
設(shè)計(jì)資源: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 846mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤(pán)
輸入數(shù)目和類(lèi)型: 4 個(gè)單端,單極;2 個(gè)差分,單極
AD9640
Rev. B | Page 6 of 52
ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
Parameter
Temperature
AD9640ABCPZ-125/
AD9640BCPZ-125
AD9640ABCPZ-150/
AD9640BCPZ-150
Unit
Min
Typ
Max
Min
Typ
Max
RESOLUTION
Full
14
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
±0.3
±0.6
±0.3
±0.6
% FSR
Gain Error
Full
±0.2
±3.0
±0.2
±3.0
% FSR
Differential Nonlinearity (DNL)1
Full
±0.9
0.95/+1.5
LSB
25°C
±0.4
0.4/+0.6
LSB
Integral Nonlinearity (INL)1
Full
±5.0
LSB
25°C
±2
LSB
MATCHING CHARACTERISTIC
Offset Error
25°C
±0.4
±0.7
±0.4
±0.7
% FSR
Gain Error
25°C
±0.1
±0.6
±0.2
±0.6
% FSR
TEMPERATURE DRIFT
Offset Error
Full
±15
ppm/°C
Gain Error
Full
±95
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
±2
±15
±3
±15
mV
Load Regulation @ 1.0 mA
Full
7
mV
INPUT REFERRED NOISE
VREF = 1.0 V
25°C
1.3
LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V
Full
2
V p-p
Input Capacitance2
Full
8
pF
VREF INPUT RESISTANCE
Full
6
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
Full
1.7
1.8
1.9
1.7
1.8
1.9
V
DRVDD (CMOS Mode)
Full
1.7
3.3
3.6
1.7
3.3
3.6
V
DRVDD (LVDS Mode)
Full
1.7
1.8
1.9
1.7
1.8
1.9
V
Supply Current
IAVDD1, 3
Full
385
470
419
517
mA
IDVDD1, 3
Full
42
50
mA
IDRVDD1 (3.3 V CMOS)
Full
44
53
mA
IDRVDD1 (1.8 V CMOS)
Full
22
27
mA
IDRVDD1 (1.8 V LVDS)
56
57
POWER CONSUMPTION
DC Input
Full
750
846
820
938
mW
Sine Wave Input1 (DRVDD = 1.8 V)
Full
810
895
mW
Sine Wave Input1 (DRVDD = 3.3 V)
Full
910
1000
mW
Standby Power4
Full
77
mW
Power-Down Power
Full
2.5
6
2.5
6
mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
3 The maximum limit applies to the combination of IAVDD and IDVDD currents.
4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK
) inactive (set to AVDD or AGND).
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