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參數(shù)資料
| 型號： | AD9551BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 40/40頁 |
| 文件大小： | 792K |
| 代理商： | AD9551BCPZ |
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AD9551
Rev. B | Page 9 of 40
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
B2
2
B3
3
4
REFA
5
REFB
6
7
RESET
8
LDO_IPDIG
9
VDD
10
LDO_XTAL
23 VDD
24 LDO_1.8
25 INPUT PLL LOCKED
26 OUTPUT PLL LOCKED
27 VDD
28 OUT2
29 OUT2
30 GND
22 LDO_VCO
21 Y0
11
X
TA
L
0
12
X
TA
L
1
13
C
S
15
S
D
IO
17
L
F
16
U
T
S
E
L
18
Y
3
19
Y
2
20
Y
1
14
S
C
L
K
33
O
U
T
1
34
V
D
35
A
0
36
A
1
37
A
2
38
A
3
39
B
0
40
B
1
32
O
U
T
1
31
G
N
D
TOP VIEW
(Not to Scale)
AD9551
PIN 1
INDICATOR
O
07
80
5-
00
3
REFA
REFB
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin
No.
Mnemonic
Description
9, 23,
27, 34
VDD
P
Power Supply Connection (3.3 V Analog Supply).
30, 31
GND
P
Analog Ground.
4
REFA
I
Analog Input (Active High)—Reference Clock Input A.
3
REFA
I
Analog Input (Active High)—Complementary Reference Clock Input A.
5
REFB
I
Analog Input (Active High)—Reference Clock Input B.
6
REFB
I
Analog Input (Active High)—Complementary Reference Clock Input B.
13
CS
I
Digital Input Chip Select (Active Low).
14
SCLK
I
Serial Data Clock.
15
SDIO
I/O
Digital Serial Data Input/Output.
7
RESET
I
Digital Input (Active High). Resets internal logic to default states. This pin has an internal 100 kΩ
pull-up resistor, so the default state of the device is reset.
11
XTL0
I
Pin for Connecting an External Crystal (20 MHz to 30 MHz).
12
XTL1
I
Pin for Connecting an External Crystal (20 MHz to 30 MHz).
33
OUT1
O
Square Wave Clocking Output 1.
32
OUT1
O
Complementary Square Wave Clocking Output 1.
29
OUT2
O
Square Wave Clocking Output 2.
28
OUT2
O
Complementary Square Wave Clocking Output 2.
17
LF
I/O
Loop Filter Node for the Output PLL. Connect an external 12 nF capacitor (100 nF in 19.44 MHz
mode) from this pin to Pin 22 ( LDO_VCO).
26
OUTPUT PLL LOCKED
O
Active High Locked Status Indicator for the Output PLL.
25
INPUT PLL LOCKED
O
Active High Locked Status Indicator for the Input PLL.
16
OUTSEL
I
Logic 0 selects LVDS, and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2
when the outputs are not under SPI port control. Can be overridden via the programming registers.
8
LDO_IPDIG
P/O
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
10
LDO_XTAL
P/O
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
22
LDO_VCO
P/O
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
24
LDO_1.8
P/O
LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground.
35
A0
I
Control Pin. Selects preset values for the REFA dividers.
36
A1
I
Control Pin. Selects preset values for the REFA dividers.
37
A2
I
Control Pin. Selects preset values for the REFA dividers.
38
A3
I
Control Pin. Selects preset values for the REFA dividers.
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