參數(shù)資料
型號(hào)： AD9548BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 111/112頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告： AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
AD9548
Data Sheet
Rev. E | Page 98 of 112
Address
Bits
Bit Name
Description
0x0A0F
[7]
Ref Mon Override DD
Overrides the reference monitor REF fault signal for Reference DD (default = 0,
not overridden).
[6]
Ref Mon Override D
Overrides the reference monitor REF fault signal for Reference D (default = 0, not
overridden).
[5]
Ref Mon Override CC
Overrides the reference monitor REF fault signal for Reference CC (default = 0, not
overridden).
[4]
Ref Mon Override C
Overrides the reference monitor REF fault signal for Reference C (default = 0, not
overridden).
[3]
Ref Mon Override BB
Overrides the reference monitor REF fault signal for Reference BB (default = 0, not
overridden).
[2]
Ref Mon Override B
Overrides the reference monitor REF fault signal for Reference B (default = 0, not
overridden).
[1]
Ref Mon Override AA
Overrides the reference monitor REF fault signal for Reference AA (default = 0, not
overridden).
[0]
Ref Mon Override A
Overrides the reference monitor REF fault signal for Reference A (default = 0, not
overridden).
0x0A10
[7]
Ref Mon Bypass DD
Bypasses the reference monitor for Reference DD (default = 0, not bypassed).
[6]
Ref Mon Bypass D
Bypasses the reference monitor for Reference D (default = 0, not bypassed).
[5]
Ref Mon Bypass CC
Bypasses the reference monitor for Reference CC (default = 0, not bypassed).
[4]
Ref Mon Bypass C
Bypasses the reference monitor for Reference C (default = 0, not bypassed).
[3]
Ref Mon Bypass BB
Bypasses the reference monitor for Reference BB (default = 0, not bypassed).
[2]
Ref Mon Bypass B
Bypasses the reference monitor for Reference B (default = 0, not bypassed).
[1]
Ref Mon Bypass AA
Bypasses the reference monitor for Reference AA (default = 0, not bypassed).
[0]
Ref Mon Bypass A
Bypasses the reference monitor for Reference A (default = 0, not bypassed).
1
See Figure 35 for details.
CLOCK PART SERIAL ID (REGISTER 0x0C00 TO REGISTER 0x0C07)
User programmable EEPROM ID registers.
Table 131. User Defined Identification Registers
Address
Bits
Bit Name
Description
0x0C00
[7:0]
User scratch pad [7:0]
User programmable EEPROM ID registers. These registers enable users to write a
unique code of their choosing to keep track of revisions to the EEPROM register
loading. It has no effect on part operation. The default EEPROM storage sequence
must be altered to include these registers. See the Programming the EEPROM to
0 = default.
0x0C01
[7:0]
User scratch pad[15:8]
0x0C02
[7:0]
User scratch pad[23:16]
0x0C03
[7:0]
User scratch pad[31:24]
0x0C04
[7:0]
User scratch pad[39:32]
0x0C05
[7:0]
User scratch pad[47:40]
0x0C06
[7:0]
User scratch pad[55:48]
0x0C07
[7:0]
User scratch pad[63:56]
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19)
All bits in Register 0x0D00 to Register 0x0D19 are read only. Register 0x0D00 and Register 0x0D01 require an IO_UPDATE
(Register 0x0005 = 0x01) in order to reflect their latest status.
Table 132. EEPROM Status
Address
Bits
Bit Name
Description
0x0D00
[7:3]
Unused
[2]
Fault detected
An error occurred while saving data to or loading data from the EEPROM.
[1]
Load in progress
The control logic sets this bit while data is being read from the EEPROM.
[0]
Save in progress
The control logic sets this bit while data is being written to the EEPROM.
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