參數(shù)資料
型號(hào)： AD9540-VCO/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/32頁
文件大?。?/td> 0K
描述： BOARD EVAL CLK GEN SYNTH 48LFCSP
設(shè)計(jì)資源： AD9540 Eval Brd Schematics
AD9540 Eval Brd BOM
AD9540 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
已用 IC / 零件： AD9540
已供物品： 板
AD9540
Rev. A | Page 22 of 32
SERIAL PORT OPERATION
An AD9540 serial data port communication cycle has two
phases. Phase 1 is the instruction cycle, writing an instruction
byte to the AD9540, coincident with the first eight SCLK rising
edges. The instruction byte provides the AD9540 serial port
controller with information regarding the data transfer cycle,
which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines the serial address of the register being
accessed and whether the upcoming data transfer is read or
write.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9540. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9540
and the system controller.
The number of bytes transferred during Phase 2 of the commu-
nication cycle is a function of the register being accessed. For
example, when accessing Control Function Register 2, which is four
bytes wide, Phase 2 requires that four bytes be transferred. If
accessing a frequency tuning word, which is six bytes wide,
Phase 2 requires that six bytes be transferred. After transferring
all data bytes per the instruction, the communication cycle is
completed.
At the completion of any communication cycle, the AD9540
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9540 is registered on the rising edge of
SCLK. All data is driven out of the AD9540 on the falling edge
of SCLK. Figure 39 through Figure 42 are useful in understand-
ing the general operation of the AD9540 serial port.
.
04947-019
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 39. Serial Port Write Timing—Clock Stall Low
04947-020
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
D5
D4
D3
D2
D1
D0
D7
D6
SDO
CS
Figure 40. 3-Wire Serial Port Read Timing—Clock Stall Low
04947-021
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 41. Serial Port Write Timing—Clock Stall High
04947-022
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 42. 2-Wire Serial Port Read Timing—Clock Stall High
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參數(shù)描述
AD9542/PCBZ
AD9542BCPZ 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包裝:托盤 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應(yīng)商器件封裝:64-LFCSP（9x9） 標(biāo)準(zhǔn)包裝:1
AD9542BCPZ-REEL7 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應(yīng)商器件封裝:64-LFCSP（9x9） 標(biāo)準(zhǔn)包裝:750
AD9543/PCBZ 功能描述:EVALUATION BOARD AD9543 制造商:analog devices inc. 系列:- 零件狀態(tài):在售 主要用途:計(jì)時(shí)，時(shí)鐘同步器 嵌入式:- 使用的 IC/零件:AD9543 主要屬性:- 輔助屬性:圖形用戶界面 所含物品:板 標(biāo)準(zhǔn)包裝:1
AD9543BCPZ 功能描述:BBU DERIVATIVE FOR AD9545 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:時(shí)鐘同步器 PLL:是 輸入:差分或單端 輸出:CML、HCSL、LVDS 或單端 電路數(shù):2 比率 - 輸入:輸出:4：10 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.4GHz 分頻器/倍頻器:是/無 電壓 - 電源:1.71 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1
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