參數(shù)資料
型號(hào)： AD9522-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 66/76頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.4GHZ 64LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9522-5
Rev. 0 | Page 69 of 76
Reg.
Addr
(Hex) Bit(s) Name
Description
0FC
[2]
CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[1]
CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[0]
CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[3]
CSDLD En
OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[2]
CSDLD En
OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[1]
CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[0]
CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 49. LVDS Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
Description
190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
190
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
191
[7]
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
191
[6]
Divider 0 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
191
[5]
Divider 0 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
191
[4]
Divider 0 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
191
[3:0]
Divider 0 phase offset
Phase offset (default: 0x0).
192
[2]
Channel 0 power-down
Channel 0 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into the high
impedance power-down mode by setting this bit.)
192
[0]
Disable Divider 0 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
193
[7:4]
Divider 1 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).
193
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).
194
[7]
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
194
[6]
Divider 1 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
194
[5]
Divider 1 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
相關(guān)PDF資料
PDF描述
X9418YP24-2.7 IC XDCP DUAL 64-TAP 2.5K 24-DIP
VI-BTK-MV-S CONVERTER MOD DC/DC 40V 150W
VI-BTJ-MV-S CONVERTER MOD DC/DC 36V 150W
AD9516-5BCPZ-REEL7 IC CLOCK GEN W/PLL 64-LFCSP
V24A24H300BL2 CONVERTER MOD DC/DC 24V 300W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9523 制造商:AD 制造商全稱:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs
AD9523/PCBZ 功能描述:BOARD EVAL FOR AD9523 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9523-1/PCBZ 功能描述:BOARD EVAL FOR AD9523-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9523-1BCPZ 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
AD9523-1BCPZ-REEL7 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*