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參數(shù)資料
| 型號： | AD9522-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.4GHZ 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9522-5
Rev. 0 | Page 67 of 76
Reg.
Addr
(Hex) Bit(s) Name
Description
01D
[5]
Enable clock
doubler
Enable PLL reference input clock doubler.
[5] = 0; doubler disabled (default).
[5] = 1; doubler enabled.
01D
[4]
Disable PLL
status register
Disables the PLL status register readback.
[4] = 0; PLL status register enabled (default).
[4] = 1; PLL status register disabled. If this bit is set, 0x01F is not automatically updated.
01D
[3]
Enable LD pin
comparator
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When the AD9522 is in internal (automatic) holdover mode, this enables the use of the voltage on the
LD pin to determine if the PLL was previously in a locked state (see Figure 34). Otherwise, this can be used
with the REFMON and STATUS pins to monitor the voltage on the LD pin.
[3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover
controller treats this pin as true (high, default).
[3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked).
01D
[1]
Enable external
holdover
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
[1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default).
[1] = 1; external holdover mode, holdover controlled by SYNC pin.
01D
[0]
Enable
holdover
Enables the internally controlled holdover function.
[0] = 0; holdover disabled (default).
[0] = 1; holdover enabled.
01E
[1]
Enable zero
delay
Enables zero delay function.
[1] = 0; disables zero delay function (default).
[1] = 1; enables zero delay function.
01F
[5]
Holdover active
(read-only)
Readback register. Indicates if the part is in the holdover state (see Figure 34). This is not the same as
holdover enabled.
[5] = 0; not in holdover.
[5] = 1; holdover state active.
01F
[4]
REF2 selected
(read-only)
Readback register. Indicates which PLL reference is selected as the input to the PLL.
[4] = 0; REF1 selected (or differential reference if in differential mode).
[4] = 1; REF2 selected.
01F
[3]
CLK frequency
> threshold
(read-only)
Readback register. Indicates if the external CLK input frequency is greater than the threshold (see Table 14,
REF1, REF2, and external CLK frequency status monitor parameter).
[3] = 0; CLK frequency is less than the threshold.
[3] = 1; CLK frequency is greater than the threshold.
01F
[2]
REF2 frequency
> threshold
(read-only)
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A[6].
[2] = 0; REF2 frequency is less than the threshold frequency.
[2] = 1; REF2 frequency is greater than the threshold frequency.
01F
[1]
REF1 frequency
> threshold
(read-only)
Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency
set by Register 0x01A[6].
[1] = 0; REF1 frequency is less than the threshold frequency.
[1] = 1; REF1 frequency is greater than the threshold frequency.
01F
[0]
Digital lock
detect
(read-only)
Readback register. Digital lock detect.
[0] = 0; PLL is not locked.
[0] = 1; PLL is locked.
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