參數(shù)資料
型號(hào)： AD9520-5BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/76頁(yè)
文件大小： 0K
描述： IC CLOCK GEN EXT VCO 64-LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9520-5
Data Sheet
Rev. A | Page 44 of 76
Soft Reset via the Serial Port
The serial port control register allows for a soft reset by setting
Bit 2 and Bit 5 in Register 0x000. The function of this register is
determined by the state of the EEPROM pin.
When Bit 2 and Bit 5 are set and the EEPROM pin is high, the chip
is restored to the settings saved in the EEPROM. When Bit 2 and
Bit 5 are set and the EEPROM pin is low, the chip is restored to
the on-chip defaults.
Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000
retains its previous value prior to reset. During the internal reset,
the outputs hold static. However, the self-clearing operation does
not complete until an additional serial port SCLK cycle occurs,
and the AD9520 is held in reset until that happens.
Soft Reset to Settings in EEPROM when EEPROM Pin = 0b
via the Serial Port
If the EEPROM pin is low, the serial port control register allows
the chip to be reset to settings in EEPROM via Register 0xB02[1].
(Bit 1 is self-clearing.) This bit does not have any effect when the
EEPROM pin is high. It takes ~20 ms for the outputs to begin
toggling after the SOFT_EEPROM register is cleared.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9520 can be put into a power-down condition by pulling
the PD pin low. Power-down turns off most of the functions and
currents inside the AD9520. The chip remains in this power-down
state until PD is brought back to logic high. When taken
out of power-down mode, the AD9520 returns to the settings
programmed into its registers prior to the power-down, unless
the registers are changed by new programming while the PD
pin is held low.
Powering down the chip shuts down the currents on the chip,
except for the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. The LVPECL bias currents are
needed to protect the LVPECL output circuitry from damage that
can be caused by certain termination and load configurations
when tristated. Because this is not a complete power-down, it
can be called sleep mode. The AD9520 contains special circuitry to
prevent runt pulses on the outputs when the chip is entering or
exiting sleep mode.
When the AD9520 is in a PD power-down, the chip is in the
following state:
The PLL is off (asynchronous power-down).
The CLK input buffer is off, but the CLK input dc bias
circuit is on.
In differential mode, the reference input buffer is off, but
the dc bias circuit is still on.
In singled-ended mode, the reference input buffer is off,
and the dc bias circuit is off.
All dividers are off.
All CMOS outputs are tristated.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
PLL Power-Down
The PLL section of the AD9520 can be selectively powered
down. There are two PLL power-down modes set by
Register 0x010[1:0]: asynchronous and synchronous.
In asynchronous power-down mode, the device powers down
as soon as the registers are updated. In synchronous power-
down mode, the PLL power-down is gated by the charge pump
to prevent unwanted frequency jumps. The device goes into power-
down on the occurrence of the next charge pump event after the
registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b, which turns off the bias to the distribution
section. If the LVPECL power-down mode is in normal operation
(Register 0x230[1] = 0b), it is possible for a low impedance load
on that LVPECL output to draw significant current during this
power-down. If the LVPECL power-down mode is set to 1b, the
LVPECL output is not protected from reverse bias and can be
damaged under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
into safe power-down mode by individually writing to the
appropriate registers. The register map details the individual
power-down settings for each output. These settings are found
in Bit 0 of Register 0x0F0 to Register 0x0FB.
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map
details the individual power-down settings for each output
channel. These settings are found in Bit 2 of Register 0x192,
Register 0x195, Register 0x198, and Register 0x19B.
相關(guān)PDF資料
PDF描述
M83723/83G1203N CONN RCPT 3POS WALL MT W/PINS
X9116WM8 IC DIGITAL POT 10K 16TP 8MSOP
MS27467E25F35SD CONN PLUG 128POS STRAIGHT W/SCKT
X9111TV14I IC DCP 100K 1024TP 14TSSOP
MS3452W28-2S CONN RCPT 14POS BOX MNT W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9520-5BCPZ-REEL7 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9521JH 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Log/Antilog Amplifier
AD9521KH 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Log/Antilog Amplifier
AD9521SE 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Log/Antilog Amplifier
AD9521SH 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Log/Antilog Amplifier
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*