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參數(shù)資料
| 型號： | AD9517-4A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-4A |
| 設(shè)計資源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-4 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-4A |
| 主要屬性： | 2 輸入，12 輸出，1.6GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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Data Sheet
AD9517-4
Rev. E | Page 75 of 80
Table 60. VCO Divider and CLK Input
Reg.
Addr
(Hex)
Bits
Name
Description
0x1E0
[2:0]
VCO divider
2
1
0
Divide
0
2.
0
1
3.
0
1
0
4 (default).
0
1
5.
1
0
6.
1
0
1
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1
0
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
0x1E1
4
Power down clock input section
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
3
Power down VCO clock interface
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
2
Power down VCO and CLK
Powers down both VCO and CLK input.
0: normal operation (default).
1: power-down.
1
Select VCO or CLK
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
0
Bypass VCO divider
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 61. System
Reg.
Addr.
(Hex)
Bits
Name
Description
0x230
2
Power down sync
Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down sync circuitry.
1
Power down distribution reference
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0
Soft sync
The soft sync bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a sync.
0: same as SYNC high (default).
1: same as SYNC low.
Table 62. Update All Registers
Reg.
Addr
(Hex)
Bits
Name
Description
0x232
0
Update all registers
This bit must be set to 1b to transfer the contents of the buffer registers into the active
registers. This bit is self-clearing; that is, it does not have to be set back to 0b.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9517-4BCPZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC CLOCK GENERATOR 1.8GHZ LFCSP-48 制造商:Analog Devices 功能描述:IC, CLOCK GENERATOR, 1.8GHZ, LFCSP-48, Clock IC Type:Clock Generator, Frequency: |
| AD9517-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9518-0 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator |
| AD9518-0/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 6-Output Clock Generator With Integrated 2.8 GHZ VCO |
| AD9518-0A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9518-0A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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