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| 型號： | AD9517-4A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 56/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-4A |
| 設(shè)計(jì)資源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-4 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-4A |
| 主要屬性： | 2 輸入，12 輸出，1.6GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9517-4
Data Sheet
Rev. E | Page 6 of 80
CLOCK INPUTS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Differential input
Input Frequency
2.4
GHz
High frequency distribution (VCO divider)
1.6
GHz
Distribution only (VCO divider bypassed)
Input Sensitivity, Differential
150
mV p-p
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Input Level, Differential
2
V p-p
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Input Common-Mode Voltage, VCM
1.3
1.57
1.8
V
Self-biased; enables ac coupling
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended
150
mV p-p
CLK ac-coupled; CLK ac-bypassed to RF ground
Input Resistance
3.9
4.7
5.7
k
Self-biased
Input Capacitance
2
pF
1
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Termination = 50 to VS 2 V
OUT0, OUT1, OUT2, OUT3
Differential (OUT, OUT)
Output Frequency, Maximum
2950
MHz
Using direct to output; see Figure 25 for peak-to-peak
differential amplitude
Output High Voltage (VOH)
VS_LVPECL
1.12
VS_LVPECL
0.98
VS_LVPECL
0.84
V
Output Low Voltage (VOL)
VS_LVPECL
2.03
VS_LVPECL
1.77
VS_LVPECL
1.49
V
Output Differential Voltage (VOD)
550
790
980
mV
This is VOH VOL for each leg of a differential pair for
default amplitude setting with driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver toggling
is roughly 2× these values (see Figure 25 for variation
over frequency)
LVDS CLOCK OUTPUTS
Differential termination 100 at 3.5 mA
OUT4, OUT5, OUT6, OUT7
Differential (OUT, OUT)
Output Frequency
800
MHz
The AD9517 outputs toggle at higher frequencies,
but the output amplitude may not meet the VOD
specification; see Figure 26
Output Differential Voltage (VOD)
247
360
454
mV
VOH VOL measurement across a differential pair at the
default amplitude setting with output driver not
toggling; see Figure 26 for variation over frequency
Delta VOD
25
mV
This is the absolute value of the difference between
VOD when the normal output is high vs. when the
complementary output is high
Output Offset Voltage (VOS)
1.125
1.24
1.375
V
(VOH + VOL)/2 across a differential pair
Delta VOS
25
mV
This is the absolute value of the difference between
VOS when the normal output is high vs. when the
complementary output is high
Short-Circuit Current (ISA, ISB)
14
24
mA
Output shorted to GND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-4BCPZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC CLOCK GENERATOR 1.8GHZ LFCSP-48 制造商:Analog Devices 功能描述:IC, CLOCK GENERATOR, 1.8GHZ, LFCSP-48, Clock IC Type:Clock Generator, Frequency: |
| AD9517-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9518-0 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator |
| AD9518-0/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 6-Output Clock Generator With Integrated 2.8 GHZ VCO |
| AD9518-0A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9518-0A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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