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| 型號： | AD9516-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 65/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9516-5 2.5GHZ |
| 產(chǎn)品培訓(xùn)模塊： | Active Filter Design Tools |
| 設(shè)計資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-5 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-5 |
| 主要屬性： | 2 輸入，14 輸出 |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
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AD9516-5
Rev. A | Page 68 of 76
Table 54. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x199
[7:4]
Low Cycles Divider 3.1
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
[3:0]
High Cycles Divider 3.1
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
0x19A
[7:4]
Phase Offset Divider 3.2
Refers to LVDS/CMOS channel divider function description (default: 0x0).
[3:0]
Phase Offset Divider 3.1
Refers to LVDS/CMOS channel divider function description (default: 0x0).
0x19B
[7:4]
Low Cycles Divider 3.2
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
[3:0]
High Cycles Divider 3.2
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
0x19C
5
Bypass Divider 3.2
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 3.1
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass (default).
1: bypasses.
3
Divider 3 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 3 force high
Forces Divider 3 output high. Requires that the Divider 3 nosync bit (Bit 3) also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 3.2
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 3.1
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
0x19D
0
Divider 3 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x19E
[7:4]
Low Cycles Divider 4.1
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
[3:0]
High Cycles Divider 4.1
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
0x19F
[7:4]
Phase Offset Divider 4.2
Refers to LVDSCMOS channel divider function description (default: 0x0).
[3:0]
Phase Offset Divider 4.1
Refers to LVDSCMOS channel divider function description (default: 0x0).
0x1A0
[7:4]
Low Cycles Divider 4.2
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
[3:0]
High Cycles Divider 4.2
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
0x1A1
5
Bypass Divider 4.2
Bypasses (and powers down) 4.2 divider logic, routes clock to 4.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 4.1
Bypasses (and powers down) 4.1 divider logic, routes clock to 4.1 output.
0: does not bypass (default).
1: bypasses.
3
Divider 4 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
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