參數(shù)資料
型號(hào)： AD9516-5/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 64/76頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9516-5 2.5GHZ
產(chǎn)品培訓(xùn)模塊： Active Filter Design Tools
設(shè)計(jì)資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-5 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-5
主要屬性： 2 輸入，14 輸出
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，CD，電源
AD9516-5
Rev. A | Page 67 of 76
Reg.
Addr.
(Hex)
Bits
Name
Description
5
Divider 1 force high
Forces divider output to high. This operation requires that the Divider 1 nosync bit (Bit 6) also
be set. This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.
0: normal operation (default).
1: divider output forced to the setting of the Divider 1 start high bit.
4
Divider 1 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 1 phase offset
Phase offset (default: 0x0).
0x195
1
Divider 1 direct to output
Connects OUT2 and OUT3 to Divider 1 or directly to CLK input.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[0] = 1b, this has no effect.
0
Divider 1 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x196
[7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays
low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays
high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
0x197
7
Divider 2 bypass
Bypasses and powers down the divider; route input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 2 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 2 force high
Forces divider output to high. This operation requires that the Divider 2 nosync bit (Bit 6) also
be set. This bit has no effect if the Divider 2 bypass bit (Bit 7) is set.
0: normal operation (default).
1: divider output forced to the setting of the Divider 2 start high bit.
4
Divider 2 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 2 phase offset
Phase offset (default: 0x0).
0x198
1
Divider 2 direct to output
Connects OUT4 and OUT5 to Divider 2 or directly to CLK input.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: if 0x1E1[0] = 0b, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1[0] = 1b, there is no effect.
0
Divider 2 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
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