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參數(shù)資料
| 型號： | AD9516-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9516-5 2.5GHZ |
| 產品培訓模塊： | Active Filter Design Tools |
| 設計資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-5 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-5 |
| 主要屬性： | 2 輸入，14 輸出 |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
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AD9516-5
Rev. A | Page 28 of 76
Phase-Locked Loop (PLL)
CLK
CHARGE PUMP
R DIVIDER
CP
VCP
VSGND
STATUS
CPRSET
DIST
REF
RSET
DIVIDE BY
2, 3, 4, 5, OR 6
A/B
COUNTERS
LD
N DIVIDER
REFMON
0
1
0
1
P, P + 1
PRESCALER
REF2
REF1
REFERENCE
SWITCHOVER
HOLD
VCO STATUS
REF_SEL
LOCK
DETECT
STATUS
CLK
PHASE
FREQUENCY
DETECTOR
PROGRAMMABLE
N DELAY
PROGRAMMABLE
R DELAY
PLL
REF
REFIN (REF1)
REFIN (REF2)
079
72-
064
Figure 35. PLL Functional Blocks
The AD9516 includes on-chip PLL blocks that can be used with
an external VCO or VCXO to create a complete phase-locked
loop. The PLL requires an external loop filter, which usually
consists of a small number of capacitors and resistors. The
configuration and components of the loop filter help to establish
the loop bandwidth and stability of the PLL.
The AD9516 PLL is useful for generating clock frequencies from a
supplied reference frequency. This includes conversion of reference
frequencies to much higher frequencies for subsequent division
and distribution. In addition, the PLL can be exploited to clean up
jitter and phase noise on a noisy reference. The exact choices of
PLL parameters and loop dynamics are very application specific.
The flexibility and depth of the PLL allow the part to be tailored
to function in many different applications and signal environments.
Configuration of the PLL
Configuration of the PLL is accomplished by programming
the various settings for the R divider, N divider, PFD polarity,
and charge pump current. The combination of these settings
determines the PLL loop bandwidth. These are managed through
by the design of the external loop filter. Successful PLL operation
and satisfactory PLL loop performance are highly dependent upon
proper configuration of the PLL settings.
The design of the external loop filter is crucial to the proper
operation of the PLL. A thorough knowledge of PLL theory and
design is helpful.
ADIsimCLK (V1.2 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9516, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD, which, in turn, determines the correct anti-
backlash pulse setting. The antibacklash pulse setting is specified
in the phase/frequency detector (PFD) parameter of Table 2.
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors the
phase and frequency relationship between its two inputs, and tells
the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the external VCO to move the VCO frequency
up or down. The CP can be set (via Register 0x010[6:4]) for high
impedance (allows holdover operation), for normal operation
(attempts to lock the PLL loop), for pump-up, or for pump-down
(test modes). The CP current is programmable in eight steps from
(nominally) 600 μA to 4.8 mA.
The exact value of the CP current LSB is set by the CPRSET
resistor, which is nominally 5.1 kΩ. If the value of the resistor
connected to the CP_RSET pin is doubled, the resulting charge
pump current range becomes 300 μA to 2.4 mA.
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| AD9517-0A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-0A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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| AD9517-0BCPZ | 制造商:Analog Devices 功能描述: |
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