參數(shù)資料
型號(hào): AD9515BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 17/28頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK DIST 2OUT PLL 32LFCSP
設(shè)計(jì)資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 扇出緩沖器(分配),除法器
PLL: 無(wú)
輸入: 時(shí)鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.6GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 776 (CN2011-ZH PDF)
配用: AD9515/PCBZ-ND - BOARD EVAL CLOCK 2CH AD9515
AD9515
Data Sheet
Rev. A | Page 24 of 28
Exposed Metal Paddle
The exposed metal paddle on the AD9515 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND).
The exposed paddle of the AD9515 package must be soldered
down. The AD9515 must dissipate heat through its exposed
paddle. The PCB acts as a heat sink for the AD9515. The PCB
attachment must provide a good thermal path to a larger heat
dissipation area, such as a ground plane on the PCB. This
requires a grid of vias from the top layer down to the ground
plane (see Figure 34). The AD9515 evaluation board
(AD9515/PCB)provides a good example of how the part
should be attached to the PCB.
05597-035
VIAS TO GND PLANE
Figure 34. PCB Land for Attaching Exposed Paddle
POWER MANAGEMENT
In some cases, the AD9515 can be configured to use less power
by turning off functions that are not being used.
The power-saving options include the following:
A divider is powered down when set to divide = 1
(bypassed).
Adjustable delay block on OUT1 is powered down when in
off mode (S0 = 0).
An unneeded output can be powered down (see Table 12
and Table 13). This also powers down the divider for that
output.
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