參數(shù)資料
型號(hào)： AD9430BSVZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 3/44頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS 3.3V100TQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.43mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD9430
Rev. E | Page 11 of 44
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
AD9430
CMOS PINOUT
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27
28 29 30 31 32 33 34 35 36
37 38 39 40 41
42
43 44 45 46 47
48 49 50
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
02
607
-004
AG
ND
AVDD
AG
ND
AG
ND
DS
+
DS
–
AVDD
AG
ND
CL
K+
CL
K–
AG
ND
AVDD
AG
ND
DN
C
DN
C
DB0
DB1
DB2
DRV
DD
DRG
ND
DB3
DB4
DRVDD
DRGND
DA4
DA3
DA2
DA1
DA0
DNC
DRGND
DNC
DCO+
DCO–
DRVDD
DRGND
OR_B
DB11
DB10
DB9
DB8
DB7
DRVDD
DRGND
DB6
DB5
DA9
DA8
DA7
DA6
DA5
AG
ND
AV
DD
AV
DD
AG
ND
AG
ND
AV
DD
AV
DD
AG
ND
AG
ND
AG
ND
AV
DD
AV
DD
AV
DD
AG
ND
AG
ND
OR
_
A
DA11
DRV
DD
DRG
ND
DA10
S5
DNC
S4
AGND
S2
S1
DNC
AVDD
AGND
SENSE
VREF
AGND
AVDD
AGND
AVDD
AGND
VIN+
VIN–
AGND
AVDD
AGND
NOTES
1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 4. CMOS Dual-Mode Pin Configuration
Table 7. CMOS Mode Pin Function Descriptions
Pin Number
Mnemonic
Description
1
S5
Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,
GND sets fS = 1.536 V p-p differential.
2, 7, 42, 43, 65, 66, 68
DNC
Do Not Connect.
3
S4
Interleaved, Parallel Select Pin. High = interleaved.
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,
87, 91, 92, 93, 96, 97, 100
AGND1
Analog Ground.
5
S2
Output Mode Select. Low = dual-port CMOS, high = LVDS.
6
S1
Data Format Select. Low = binary, high = twos complement for
both CMOS and LVDS modes.
8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,
95, 98, 99
AVDD
3.3 V Analog Supply.
10
SENSE
Reference Mode Select Pin. Float for internal reference operation.
11
VREF
1.235 V Reference I/O—Function Dependent on SENSE.
21
VIN+
Analog Input—True.
22
VIN–
Analog Input—Complement.
32
DS+
Data Sync (Input)—True. Tie low if not used.
33
Data Sync (Input)—Complement. Tie high if not used.
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