參數(shù)資料
型號(hào)： AD9430BSVZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS 3.3V100TQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.43mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，單極
AD9430
Rev. E | Page 23 of 44
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level
(–40 dBFS) signal when the adjacent interfering channel is
driven by a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is
180° out of phase. Peak-to-peak differential is computed by
rotating the input phase 180° and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
6.02
dB
1.76
=
MEASURED
SNR
ENOB
ENCODE Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time the ENCODE
pulse (clock pulse) should be left in a Logic 1 state to achieve
rated performance; pulse width low is the minimum time the
ENCODE pulse should be left in a low state. See the timing
implications of changing tEH in the Encode Input section. At
a given clock rate, these specifications define an acceptable
ENCODE duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
=
001
.
0
log
10
2
INPUT
rms
SCALE
FULL
SCALE
FULL
Z
V
Power
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The ENCODE rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK– and
the time when all output data bits are within valid logic levels.
Noise (for Any Range Within the ADC)
Calculated as follows:
×
=
10
001
.
0
dBFS
dBc
dBM
NOISE
Signal
SNR
FS
Z
V
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value of the particular input level.
Signal is the signal level within the ADC, reported in dB below
full scale. This value includes input levels both thermal and
quantization noise.
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