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| 型號： | AD9430BSVZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS 3.3V100TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.43mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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12-Bit, 170/210 MSPS
3.3 V A/D Converter
AD9430
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005–2010 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS
ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.3 LSB (typical)
INL = ±0.5 LSB (typical)
2 output data options:
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS
Interleaved or parallel data output option
LVDS at 210 MSPS
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.3 W typical @ 210 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Data sync input and data clock output provided
Clock duty cycle stabilizer
GENERAL DESCRIPTION
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The product operates up to a 210 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a track-and-hold (T/H) and
reference, are included on the chip to provide a complete
conversion solution.
The ADC requires a 3.3 V power supply and a differential
ENCODE clock for full performance operation. The digital
outputs are TTL/CMOS or LVDS compatible and support either
twos complement or offset binary format. Separate output
power supply pins support interfacing with 3.3 V CMOS logic.
Two output buses support demultiplexed data up to 105 MSPS
rates in CMOS mode. A data sync input is supported for proper
output data port alignment in CMOS mode, and a data clock
output is available for proper output data timing. In LVDS
mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100-lead, surface-mount plastic package
(100 e-PAD TQFP) specified over the industrial temperature
range (–40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
TRACK-
AND-HOLD
SCALABLE
REFERENCE
ADC
12-BIT
PIPELINE
CORE
LVDS
OUTPUTS
CLOCK
MANAGEMENT
SENSE
VREF
AGND DRGND DRVDD AVDD
DATA,
OVERRANGE
IN LVDS OR
2-PORT CMOS
DCO–
S5
S4
S2
S1
CLK+
DS+
VIN+
AD9430
12
VIN–
DS–
CLK–
DCO+
SELECT CMOS
OR LVDS
CMOS
OUTPUTS
02607-001
Figure 1.
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
PRODUCT HIGHLIGHTS
1.
High performance.
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
2.
Low power.
Consumes only 1.3 W @ 210 MSPS.
3.
Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 3.3 V supply simplifies system power supply
design.
4.
Out of range (OR) feature.
The OR output bit indicates when the input signal is
beyond the selected input range.
5.
Pin compatible with 10-bit AD9411 (LVDS only).
.
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