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參數(shù)資料
| 型號： | AD9289BBC |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT QUAD 65MSPS 64CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 625mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 64-CSPBGA（8x8） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極 |
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AD9289
Rev. 0 | Page 15 of 32
An internal reference buffer creates the positive and negative
reference voltages, REFT and REFB, respectively, that defines
the span of the ADC core. The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range, as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved by setting the AD9289
to the largest input span of 2 V p-p.
The SHA should be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined in Figure 26 and Figure 27.
Differential Input Configurations
Optimum performance is achieved by driving the AD9289 in a
differential input configuration. For baseband applications, the
AD8351 differential driver provides excellent performance and
a flexible interface to the ADC (see Figure 28).
AD8351
GP1
VCM
PWUP
GP2
1.2k
25
1k
1k
10k
0.1
F
10
1k
1k
03682-
054
AD9289
VIN–
VIN+
AVDD
AGND
R
C
0.1
F
0.1
F
1V p-p
10
50
25
0.1
F
0.1
F
AVDD
1k
1k
Figure 28. Differential Input Configuration Using the AD8351
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9289. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. An
example of this is shown in Figure 29.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
03682-053
AD9289
VIN+
VIN–
AVDD
AGND
2Vp-p
R
C
49.9
0.1
F
1k
1k
AVDD
Figure 29. Differential Transformer-Coupled Configuration
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 30 details a typical single-
ended input configuration.
03682-052
2V p-p
R
C
49.9
0.1
F
10
F
10
F
0.1
F
AD9289
VIN+
VIN–
AVDD
AGND
AVDD
1k
1k
1k
1k
Figure 30. Single-Ended Input Configuration
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Typically, a 5% tolerance is
required on the clock duty cycle to maintain dynamic perfor-
mance characteristics. The AD9289 has a self-contained clock
duty cycle stabilizer that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows a wide range of clock input duty cycles
without affecting the performance of the AD9289.
An on-board phase-locked loop (PLL) multiplies the input
clock rate for the purpose of shifting the serial data out. As a
result, any change to the sampling frequency requires a
minimum of 100 clock periods to allow the PLL to reacquire
and lock to the new rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9289BBC-65 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9289BBC-65EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| AD9289BBCZ | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 8-bit Serial 64-Pin CSP-BGA |
| AD9300 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 x 1 Wideband Video Multiplexer |
| AD9300KP | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:4-CHANNEL, VIDEO MULTIPLEXER, PQCC20 |
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