參數(shù)資料
型號： AD9289BBC
廠商： Analog Devices Inc
文件頁數(shù)： 30/32頁
文件大?。?/td> 0K
描述： IC ADC 8BIT QUAD 65MSPS 64CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 8
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 625mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 64-CSPBGA（8x8）
包裝： 托盤
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極
AD9289
Rev. 0 | Page 7 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03682-005
H
G
F
E
D
C
B
A
1 234 567 8
Figure 3. BGA Top View (Looking Through)
Table 6. Pin Function Descriptions
Pin
No.
Mnemonic
Description
A1
D1–A
ADC A Complement Digital Output
B1
D1+A
ADC A True Digital Output
C1
FCO+
Frame Clock Output (MSB Indicator)
True Output
D1
DNC
Do Not Connect
E1
AGND
Analog Ground
F1
VIN–A
ADC A Analog Input—Complement
G1
VIN+A
ADC A Analog Input—True
H1
LVDSBIAS1
LVDS Output Bias Pin
A2
DNC
Do Not Connect
B2
DNC
Do Not Connect
C2
FCO–
Frame Clock Output (MSB Indicator)
Complement Output
D2
DNC
Do Not Connect
E2
AGND
Analog Ground
F2
AVDD
Analog Supply
G2
AGND
Analog Ground
H2
VIN+B
ADC B Analog Input—True
A3
D1–B
ADC B Complement Digital Output
B3
D1+B
ADC B True Digital Output
C3
DRVDD
Digital Supply
D3
DRGND
Digital Ground
E3
AGND
Analog Ground
F3
CML
Common Mode Level Output ( = AVDD/2)
G3
SHARED_REF3
Shared Reference Control Bit
H3
VIN–B
ADC B Analog Input—Complement
A4
DNC
Do Not Connect
B4
DNC
Do Not Connect
C4
DCO+
Data Clock Output—True
D4
LOCK
PLL Lock Output
E4
AVDD
Analog Supply
F4
REFT_A
Reference Buffer Decoupling (Positive)
G4
REFB_A
Reference Buffer Decoupling (Negative)
H4
SENSE
Reference Mode Selection
A5
D1–C
ADC C Complement Digital Output
B5
D1+C
ADC C True Digital Output
C5
DCO–
Data Clock Output—Complement
Pin
No.
Mnemonic
Description
D5
AGND
Analog Ground
E5
AGND
Analog Ground
F5
REFT_B
Reference Buffer Decoupling (Positive)
G5
REFB_B
Reference Buffer Decoupling (Negative)
H5
VREF
Voltage Reference Input/Output
A6
DNC
Do Not Connect
B6
DNC
Do Not Connect
C6
DRVDD
Digital Supply
D6
DRGND
Digital Ground
E6
AVDD
Analog Supply
F6
AGND
Analog Ground
G6
AGND
Analog Ground
H6
VIN–C
ADC C Analog Input—Complement
A7
D1–D
ADC D Complement Digital Output
B7
D1+D
ADC D True Digital Output
C7
DFS2
Data Format Select
D7
AGND
Analog Ground
E7
AGND
Analog Ground
F7
AVDD
Analog Supply
G7
AGND
Analog Ground
H7
VIN+C
ADC C Analog Input—True
A8
DNC
Do Not Connect
B8
DNC
Do Not Connect
C8
CLK+
Input Clock—True
D8
CLK–
Input Clock—Complement
E8
PDWN3
Power Down Selection
F8
VIN–D
ADC D Analog Input—Complement
G8
VIN+D
ADC D Analog Input—True
H8
DTP3, 4
Digital Test Pattern
1 LVDSBIAS use a 3.9 k resistor-to-analog ground to set the LVDS output
differential swing of 350 mV p-p.
2 DFS has an internal on-chip pull-down resistor and defaults to offset binary
output coding if untied. If twos complement output coding is desired then
tie this pin to AVDD.
3 To enable, tie this pin to AVDD. To disable, tie this pin to AGND.
4 DTP has an internal on-chip pull-down resistor.
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