參數(shù)資料
型號(hào): AD9278BBCZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 32/44頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 50MSPS 144CSPBGA
標(biāo)準(zhǔn)包裝: 1
類型: AAF,ADC,解調(diào)器,LNA,VGA
分辨率(位): 12 b
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
電壓電源: 模擬和數(shù)字
電源電壓: 1.7 V ~ 1.9 V,2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 144-CSPBGA(10x10)
包裝: 托盤
AD9278
Data Sheet
Rev. A | Page 38 of 44
This interface is flexible enough to be controlled by either serial
PROMs or PIC microcontrollers, providing the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
SDIO
SCLK
CSB
tS
tDH
tHIGH
tCLK
tLOW
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
09
42
4-
06
9
Figure 66. Serial Timing Details
Table 18. Serial Timing Definitions
Parameter
Timing (ns min)
Description
tDS
5
Setup time between the data and the rising edge of SCLK
tDH
2
Hold time between the data and the rising edge of SCLK
tCLK
40
Period of the clock
tS
5
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHIGH
16
Minimum period that SCLK should be in a logic high state
tLOW
16
Minimum period that SCLK should be in a logic low state
tEN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 66)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 66)
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