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| 型號： | AD9278BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 50MSPS 144CSPBGA |
| 標準包裝： | 1 |
| 類型： | AAF，ADC，解調(diào)器，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.7 V ~ 1.9 V，2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 144-CSPBGA（10x10） |
| 包裝： | 托盤 |
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AD9278
Data Sheet
Rev. A | Page 30 of 44
09424-
064
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
5.0ns/DIV
Figure 59. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on regular FR-4 material
is shown in Figure 60. Figure 61 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine whether the waveforms meet the timing
budget of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (and, therefore, increase the current) of all
eight outputs to drive longer trace lengths (see Figure 62). Even
though this produces sharper rise and fall times on the data
edges, is less prone to bit errors, and improves frequency
distribution (see Figure 62), the power dissipation of the
DRVDD supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, set the appro-
priate bit in Register 0x05. Note that this feature cannot be used
with Bits[5:4] in Register 0x15 because these bits take precedence
over this feature. See Table 19 for more details.
The format of the output data is offset binary by default. Table 12
provides an example of the output coding format. To change the
output data format to twos complement, see the Memory Map
section.
Table 12. Digital Output Coding
Code
(VIN+) (VIN),
Input Span = 2 V p-p (V)
Digital Output
Offset Binary (D11 to D0)
4095
+1.00
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000488
0111 1111 1111
0
1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 19 for details on enabling this
feature.
09424-
065
600
400
–200
200
–100
100
–400
–600
0
–1.5ns
–0.5ns
–1.0ns
0ns
0.5ns
1.0ns
1.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 2398/2398
25
0
5
10
15
20
–200ps
–100ps
0ps
100ps
200ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4
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