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| 型號： | AD9278BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 50MSPS 144CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | AAF，ADC，解調(diào)器，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.7 V ~ 1.9 V，2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 144-CSPBGA（10x10） |
| 包裝： | 托盤 |
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AD9278
Data Sheet
Rev. A | Page 36 of 44
For CW Doppler operation, the AD9278 integrates the LNA,
phase shifter, frequency conversion, and I/Q demodulation
into a single package and directly yields the baseband signal.
Figure 64 is a simplified diagram showing the concept for four
channels. The ultrasound wave (US wave) is received by four
transducer elements, TE1 through TE4, in an ultrasound probe
and generates signals E1 through E4. In this example, the phase
at TE1 leads the phase at TE2 by 45°.
In a real application, the phase difference depends on the
element spacing, wavelength (λ), speed of sound, angle of
incidence, and other factors. In Figure 64, the signals E1
through E4 are amplified by the low noise amplifiers. For
optimum signal-to-noise performance, the output of the LNA
is applied directly to the input of the demodulators. To sum the
signals E1 through E4, E2 is shifted 45° relative to E1 by setting
the phase code in Channel 2 to 0010, E3 is shifted 90° (0100), and
E4 is shifted 135° (0110). The phase aligned current signals at
the output of the AD9278 are summed in an I-to-V converter to
provide the combined output signal with a theoretical improve-
ment in dynamic range of 6 dB for the four channels.
CW Application Information
The RESET pin is used to synchronize the LO dividers in AD9278
arrays. Because they are driven by the same internal LO, the four
channels in any AD9278 are inherently synchronous. However,
when multiple AD9278s are used, it is possible that their dividers
wake up in different phase states. The function of the RESET
pin is to phase align all the LO signals in multiple AD9278s.
The 4LO divider of each AD9278 can be initiated in one of four
possible states: 0°, 90°, 180°, and 270° relative to other AD9278s.
The internally generated I/Q signals of each AD9278 LO are always
at a 90° angle relative to each other, but a phase shift can occur
during power-up between the dividers of multiple AD9278s
used in a common array.
The RESET mechanism also allows the measurement of non-
mixing gain from the RF input to the output. The rising edge of
the active high RESET pulse can occur at any time; however, the
duration should be ≥ 20 ns minimum. When the RESET pulse
transitions from high to low, the LO dividers are reactivated on
the next rising edge of the 4LO clock. To guarantee synchronous
operation of an array of AD9278s, the RESET pulse must go low
on all devices before the next rising edge of the 4LO clock.
Therefore, it is best to have the RESET pulse go low on the falling
edge of the 4LO clock; at the very least, the tSETUP should be ≥ 5 ns.
An optimal timing setup is for the RESET pulse to go high on a
4LO falling edge and to go low on a 4LO falling edge; this gives
15 ns of setup time even at a 4LO frequency of 32 MHz (8 MHz
internal LO). Use the following procedure to check the synch-
ronization of multiple AD9278s:
1. Activate at least one channel per AD9278 by setting the
appropriate channel enable bit in the serial interface.
2. Set the phase code of all AD9278 channels to the same
logic state, for example, 0000.
3. Apply the same test signal to all devices to generate a sine
wave in the baseband output and measure the output of
one channel per device.
4. Apply a RESET pulse to all AD9278s.
5. Because all phase codes of the AD9278s should be the
same, the combined signal of multiple devices should be N
times greater than a single channel. If the combined signal
is less than N times one channel, one or more of the LO
phases of the individual AD9278s are in error.
S1
S2
S3
S4
E1
E2
E3
E4
90°
45°
135°
0 °
SUMMED
OUTPUT
S1 + S2 + S3 + S4
S1 THROUGH S4
ARE NOW
IN PHASE
PHASE BIT
SETTINGS
CHANNEL 1
PHASE SET
FOR 135°
LAG
CHANNEL 2
PHASE SET
FOR 90°
LAG
CHANNEL 3
PHASE SET
FOR 45°
LAG
CHANNEL 4
PHASE SET
FOR 0°
LAG
TRANSDUCER ELEMENT TE1
THROUGH ELEMENT TE4
CONVERT US WAVES TO
ELECTRICAL SIGNALS
LNA
4 US WAVES
ARE DELAYED
45° EACH WITH
RESPECT TO
EACH OTHER
09424-
046
Figure 64. Simplified Example of the AD9278 Phase Shifter
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| AD9279BBCZ | 功能描述:IC ADC 12BIT 80MSPS 144CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD9279-BBCZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator |
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