參數(shù)資料
型號： AD9269BCPZRL7-20
廠商： Analog Devices Inc
文件頁數(shù)： 29/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS DL 64LFCSP
標準包裝： 750
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 2
功率耗散（最大）： 102mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
AD9269
Rev. 0 | Page 35 of 40
Bit 1—Open
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
QEC Control 0 (Register 0x110)
Bits[7:6]—Open
Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain
These bits can be used to freeze the corresponding dc, phase,
and gain offset corrections of the quadrature error correction
(QEC) independently. When asserted high, QEC is applied
using frozen values, and the estimation of the quadrature errors
is halted.
Bits[2:0]—DC Enable/Phase Enable/Gain Enable
These bits allow the corresponding dc, phase, and gain offset
corrections to be enabled independently.
QEC Control 1 (Register 0x111)
Bits[7:3]—Open
Bit 2—Force DC
When set high, this bit forces the initial static correction values
from Register 0x11A and Register 0x11B for the I data and
Register 0x11C and Register 0x11D for the Q data.
Bit 1—Force Phase
When set high, this bit forces the initial static correction values
from Register 0x118 and Register 0x119.
Bit 0—Force Gain
When set high, this bit forces the initial static correction values
from Register 0x116 and Register 0x117.
QEC Gain Bandwidth Control (Register 0x112)
Bits[7:5]—Open
Bits[4:0]—KEXP_GAIN
These bits adjust the time constants of the gain control feedback
loop for quadrature error correction.
QEC Phase Bandwidth Control (Register 0x113)
Bits[7:5]—Open
Bits[4:0]—KEXP_PHASE
These bits adjust the time constants of the phase control
feedback loop for quadrature error correction.
QEC DC Bandwidth Control (Register 0x114)
Bits[7:5]—Open
Bits[4:0]—KEXP_DC
These bits adjust the time constants of the dc control feedback
loop for quadrature error correction.
QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and
Register 0x117)
Bits[14:0]—Initial Gain
When the force gain bit (Register 0x111, Bit 0) is set high, these
values are used for gain error correction.
QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and
Register 0x119)
Bits[12:0]—Initial Phase
When the force phase bit (Register 0x111, Bit 1) is set high,
these values are used for phase error correction.
QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and
Register 0x11B)
Bits[13:0]—Initial DC I
When the force dc bit (Register 0x111, Bit 2) is set high, these
values are used for dc error correction.
QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and
Register 0x11D)
Bits[13:0]—Initial DC Q
When the force dc bit (Register 0x111, Bit 2) is set high, these
values are used for dc error correction.
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