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參數(shù)資料
| 型號(hào)： | AD9269BCPZRL7-20 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 20MSPS DL 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 102mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極；2 個(gè)差分，單極；2 個(gè)差分，雙極 |
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AD9269
Rev. 0 | Page 23 of 40
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
100
0.1F
240
240
50k
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
0
853
8-
01
9
Figure 51. Differential PECL Sample Clock (Up to 480 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 52. The AD9510/
clock drivers offer excellent jitter performance.
100
0.1F
50k
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
0
853
8-
020
Figure 52. Differential LVDS Sample Clock (Up to 480 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
OPTIONAL
100
0.1F
50
1
150
RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
08
53
8-
02
1
Figure 53. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9269 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 6.
Optimum performance is obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
The AD9269 clock divider can be synchronized using the external
SYNC input. Bits[2:1] in Register 0x100 allow the clock divider
to be resynchronized on every SYNC signal or only on the first
SYNC signal after the register is written. A valid SYNC causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned
to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9269 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9269. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 54.
80
79
78
77
76
70
71
72
73
74
75
30
35
40
45
50
55
60
65
70
S
N
R
(
d
BF
S
)
POSITIVE DUTY CYCLE (%)
08
53
8-
0
64
DCS OFF
DCS ON
Figure 54. SNR vs. Duty Cycle Stabilizer On/Off
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after the dynamic clock frequency increases or decreases
before the DCS loop is relocked to the input signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9269BCPZRL7-40 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 40 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9269BCPZRL7-65 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 65 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9269BCPZRL7-80 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 80 Msps low pwr dual ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9271 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
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