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參數(shù)資料
| 型號： | AD9267BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MOD SIGMA-DELTA DUAL 64LFCSP |
| 標(biāo)準包裝： | 1 |
| 類型： | 三角積分調(diào)制器 |
| 應(yīng)用： | 無線通信系統(tǒng) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
AD9267
Rev. 0 | Page 5 of 24
DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = 2.0 dBFS,
unless otherwise noted.
Table 3.
Parameter
Temp
Min
Typ
Max
Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS1/LVDS/LVPECL
Differential Input Voltage
Full
0.4
0.8
2
V p-p
Input Common-Mode Range
Full
450
mV
High Level Input Current
Full
60
+60
μA
Low Level Input Current
Full
60
+60
μA
Input Resistance
Full
20
kΩ diff
Input Capacitance
Full
1
pF
LOGIC INPUTS (SCLK)
High Level Input Voltage
Full
1.2
DRVDD + 0.3
V
Low Level Input Voltage
Full
0
0.8
V
High Level Input Current
Full
50
75
μA
Low Level Input Current
Full
10
+10
μA
Input Resistance
Full
30
kΩ
Input Capacitance
Full
2
pF
LOGIC INPUTS (SDIO, CSB, RESET)
High Level Input Voltage
Full
1.2
DRVDD + 0.3
V
Low Level Input Voltage
Full
0
0.8
V
High Level Input Current
Full
10
+10
μA
Low Level Input Current
Full
+40
+135
μA
Input Resistance
Full
26
kΩ
Input Capacitance
Full
5
pF
DIGITAL OUTPUTS (D0±x to D3±x)
ANSI-644
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
V
Output Coding (Default)
Twos complement
Low Power, Reduced Signal Option
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
V
Output Coding (Default)
Twos complement
1 For voltage swings beyond the specified range, clamping diodes are recommended.
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