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參數(shù)資料
| 型號： | AD9267BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MOD SIGMA-DELTA DUAL 64LFCSP |
| 標準包裝： | 1 |
| 類型： | 三角積分調(diào)制器 |
| 應用： | 無線通信系統(tǒng) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
AD9267
Rev. 0 | Page 19 of 24
SERIAL PORT INTERFACE (SPI)
The AD9267 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This provides the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that are further divided into
fields, as documented in the Memory Map section. For detailed
operational information, see the see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
As summarized in Table 13, three pins define the SPI of this
ADC. The SCLK pin synchronizes the read and write data
presented to the ADC. The SDIO pin allows data to be sent and
read from the internal ADC memory map registers. The CSB
pin is an active low control that enables or disables the read and
write cycles.
Table 13. Serial Port Interface Pins
Pin
Function
SCLK
SCLK (serial clock) is the serial shift clock. SCLK
synchronizes serial interface reads and writes.
SDIO
SDIO (serial data input/output) is an input and output
depending on the instruction being sent and the
relative position in the timing frame.
CSB
CSB (chip select) is an active low control that gates the
read and write cycles.
The falling edge of CSB in conjunction with the rising edge of
the SCLK determines the start of the framing. Figure 42 and
Table 14 provide an example of the serial timing and its
definitions.
Other modes involving CSB are available. CSB can be held low
indefinitely to permanently enable the device (this is called
streaming). CSB can stall high between bytes to allow for
additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit words.
The first bit of each individual byte of serial data indicates whether
a read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as to read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an
output at the appropriate point in the serial frame.
Data can be sent in MSB- or in LSB-first mode. MSB first is
the default setting on power-up and can be changed via the
configuration register. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 14. SPI Timing Diagram Specifications
Parameter
Definition
tSDS
Setup time between data and rising edge of SCLK
tSDH
Hold time between data and rising edge of SCLK
tSCLK
Period of the clock
tSS
Setup time between CSB and SCLK
tSH
Hold time between CSB and SCLK
tSHIGH
Minimum period that SCLK should be in a logic
high state
tSLOW
Minimum period that SCLK should be in a logic
low state
DON’T CARE
SDIO
SCLK
CSB
tSS
tSDH
tSHIGH
tSCLK
tSLOW
tSDS
tSH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
0
777
3-
03
6
Figure 42. Serial Port Interface Timing Diagram
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| AD9267BCPZRL7 | 功能描述:IC MOD SIGMA-DELTA DUAL 64LFCSP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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