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參數(shù)資料
| 型號： | AD9230BCPZ11-200 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 11-BIT 200MSPS 56-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 373mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | AD923011-200EBZ-ND - BOARD EVAL FOR AD9230 200MSPS |
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AD9230-11
Rev. 0 | Page 22 of 28
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and ADC functions map
(Address 0x08 to Address 0x2A).
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, the clock register, has a hexadecimal default value
of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI, at
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 13. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of logic level terminology follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
TRANSFER REGISTER MAP
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer
bit. This allows these registers to be updated internally and
simultaneously when the transfer bit is set. The internal update
takes place when the transfer bit is set, and the bit autoclears.
Table 13. Memory Map Register
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Notes/
Comments
Chip Configuration Registers
0x00
chip_port_config
0
LSB
first
Soft
reset
1
Soft
reset
LSB first
0
0x18
The nibbles should
be mirrored by the
user so that LSB-or
MSB-first mode
registers correctly,
regardless of shift
mode.
0x01
chip_id
8-bit chip ID, Bits[7:0]
AD9230-11 = 0x0C
Read-
only
Default is unique
chip ID, different
for each device.
This is a read-only
register.
0x02
chip_grade
0
Speed grade:
11 = 200 MSPS
X
Read-
only
Child ID used to
differentiate
graded devices.
Transfer Register
0xFF
device_update
0
SW
transfer
0x00
Synchronously
transfers data from
the master shift
register to the
slave.
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