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參數(shù)資料
| 型號： | AD9230BCPZ11-200 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 11-BIT 200MSPS 56-LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 373mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | AD923011-200EBZ-ND - BOARD EVAL FOR AD9230 200MSPS |
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AD9230-11
Rev. 0 | Page 19 of 28
600
–600
–400
–200
0
200
400
–3
–2
–1
0123
VO
L
T
A
G
E
(
m
V
)
TIME (ns)
12
10
8
6
4
2
0
–100
0
100
T
IE
J
IT
T
ER
H
IST
O
G
R
A
M
(H
it
s)
TIME (ps)
07
10
1-
02
4
Figure 31. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
ment, see the Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9230-11. The DCO is used to clock the output
data and is equal to the sampling clock (CLK) rate. In single
data rate mode (SDR), data is clocked out of the AD9230-11
and must be captured on the rising edge of the DCO. In double
data rate mode (DDR), data is clocked out of the AD9230-11
and must be captured on the rising and falling edges of the
for more information.
Output Data Rate and Pinout Configuration
The output data of the AD9230-11 can be configured to drive
12 pairs of LVDS outputs at the same rate as the input clock
signal (single data rate, or SDR, mode), or six pairs of LVDS
outputs at 2× the rate of the input clock signal (double data rate,
or DDR, mode). SDR is the default mode; the device can be
reconfigured for DDR by setting Bit 3 in Register 14 (see Table 13).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data. OR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 32. OR remains high until the analog input returns to
within the input range and another conversion is completed. By
logically AND-ing OR with the MSB and its complement, over-
range high or underrange low conditions can be detected.
1
0
1
OR DATA OUTPUTS
OR
+FS – 1 LSB
+FS – 1/2 LSB
+FS
–FS
–FS + 1/2 LSB
–FS – 1/2 LSB
1111
0000
1111
0000
07
10
1-
0
25
Figure 32. OR Relation to Input Voltage and Output Data
TIMING
The AD9230-11 provides latched data outputs with a pipeline
delay of seven clock cycles. Data outputs are available one
propagation delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230-11.
These transients can degrade the dynamic performance of the
converter. The AD9230-11 also provides data clock output (DCO)
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO.
The lowest typical conversion rate of the AD9230-11 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230-11 assumes the
standby mode.
RBIAS
The AD9230-11 requires the user to place a 10 kΩ resistor
between the RBIAS pin and ground. This resister should have
a 1% tolerance and is used to set the master current reference
of the ADC core.
CONFIGURATION USING THE SPI
The AD9230-11 SPI allows the user to configure the converter for
specific functions or operations through a structured register space
inside the ADC. This gives the user added flexibility to customize
device operation depending on the application. Addresses are
accessed (programmed or readback) serially in 1-byte words. Each
byte may be further divided down into fields, which are
documented in the Memory Map section.
There are three pins that define the serial port interface (SPI) to this
particular ADC. They are the SCLK/DFS, SDIO/DCS, and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the read
and write data presented to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB pin is
an active low control that enables or disables the read and write
cycles (see Table 9).
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