參數(shù)資料
型號： AD923011-200EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/28頁
文件大小： 0K
描述： BOARD EVAL FOR AD9230 200MSPS
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 11
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行
輸入范圍： 1.0 ~ 1.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 373mW @ 200MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9230-11
已供物品： 板
相關(guān)產(chǎn)品： AD9230BCPZ11-200-ND - IC ADC 11-BIT 200MSPS 56-LFCSP
AD9230-11
Rev. 0 | Page 17 of 28
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230-11 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 24 shows a preferred method for clocking the AD9230-11.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9230-11 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230-11 and preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1F
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9230-11
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
07
10
1
-01
7
Figure 24. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple
a differential PECL signal to the sample clock input pins as
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
100
0.1F
240
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
*50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9230-11
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
07
10
1-
0
18
50*
Figure 25. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
100
0.1F
50*
CLK
*50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9230-11
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
07
10
1-
01
9
Figure 26. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 27). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V (as shown in
Figure 28), making the selection of the drive logic voltage very
flexible.
0.1F
39k
CMOS DRIVER
50*
OPTIONAL
100
0.1F
CLK
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9230-11
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
07
10
1-
0
20
Figure 27. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CMOS DRIVER
CLK
*50 RESISTOR IS OPTIONAL.
0.1F
CLK–
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
ADC
AD9230-11
CLOCK
INPUT
50*
OPTIONAL
100
07
10
1-
02
1
Figure 28. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9230-11 contains a duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the perform-
ance of the AD9230-11. When the DCS is on, noise and distortion
performance are nearly flat for a wide range of duty cycles.
However, some applications may require the DCS function to
be off. If so, keep in mind that the dynamic range performance can
be affected when operated in this mode. See the Configuration
Using the SPI section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9230-170EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter
AD9230-170EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12-Bit 170 Msps ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
AD9230-210EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter
AD9230-210EBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12-Bit 210 Msps ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
AD9230-250EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter
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