- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17024 > AD923011-200EBZ (Analog Devices Inc)BOARD EVAL FOR AD9230 200MSPS PDF資料下載
參數(shù)資料
| 型號(hào)： | AD923011-200EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9230 200MSPS |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.0 ~ 1.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 373mW @ 200MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9230-11 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9230BCPZ11-200-ND - IC ADC 11-BIT 200MSPS 56-LFCSP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
AD9230-11
Rev. 0 | Page 16 of 28
THEORY OF OPERATION
The AD9230-11 architecture consists of a front-end sample-
and-hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 11-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample, while the remaining stages operate
on preceding samples. Sampling occurs on the rising edge of the
clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a buffered differential SHA that can
be ac- or dc-coupled. The output staging block aligns the data,
carries out the error correction, and passes the data to the out-
put buffers. The output buffers are powered from a separate
supply, allowing adjustment of the output voltage swing. During
power-down, the output buffers go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9230-11 is a differential buffer. For
best dynamic performance, the source impedances driving
VIN+ and VIN should be matched such that common-mode
settling errors are symmetrical. The analog input is optimized
to provide superior wideband performance and requires that
the analog inputs be driven differentially. SNR and SINAD
performance degrades significantly if the analog input is driven
with a single-ended signal.
A wideband transformer, such as Mini-Circuits ADT1-1WT, can
provide the differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs are self-
biased by an on-chip resistor divider to a nominal 1.4 V. An
internal differential voltage reference creates positive and negative
reference voltages that define the 1.25 V p-p fixed span of the ADC
core. This internal voltage reference can be adjusted by means of
SPI control. See the Configuration Using the SPI section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9230-11
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
VIN+
VIN–
AVDD
CML
AD8138
523
499
33
49.9
1V p-p
0.1F
20pF
AD9230-11
0
71
01
-0
14
Figure 21. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve the
true performance of the AD9230-11. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications, differen-
tial transformer coupling is the recommended input configuration.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies below a
few megahertz and excessive signal power can also cause core
saturation, leading to distortion. In any configuration, the value of
the shunt capacitor, C, is dependent on the input frequency and
may need to be reduced or removed.
VIN+
VIN–
15
50
1.25V p-p
0.1F
2pF
AD9230-11
07
10
1-
0
15
Figure 22. Differential Transformer—Coupled Configuration
As an alternative to using a transformer-coupled input at frequen-
cies in the second Nyquist zone, the AD8352 differential driver can
be used (see Figure 23).
AD9230-11
AD8352
0
R
0
CD
RD
RG
0.1F
VIN+
VIN– CML
C
0.1F
16
1
2
3
4
5
11
R
0.1F
10
8, 13
14
VCC
200
ANALOG INPUT
071
01-
01
6
Figure 23. Differential Input Configuration Using the AD8352
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HW-V5-ML523-UNI-G-J | EVALUATION PLATFORM VIRTEX-5 |
| AD9228-65EBZ | BOARD EVAL FOR AD9228 |
| GSM10DRST | CONN EDGECARD 20POS DIP .156 SLD |
| STD21W-A | WIRE & CABLE MARKERS |
| DK-SI-5SGXEA7N | KIT DEV STRATIX V FPGA 5SGXEA7 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9230-170EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter |
| AD9230-170EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12-Bit 170 Msps ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9230-210EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter |
| AD9230-210EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12-Bit 210 Msps ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9230-250EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。