參數(shù)資料
型號: AD923011-200EBZ
廠商: Analog Devices Inc
文件頁數(shù): 16/28頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9230 200MSPS
標準包裝: 1
ADC 的數(shù)量: 1
位數(shù): 11
采樣率(每秒): 200M
數(shù)據(jù)接口: 串行
輸入范圍: 1.0 ~ 1.5 V
在以下條件下的電源(標準): 373mW @ 200MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9230-11
已供物品:
相關(guān)產(chǎn)品: AD9230BCPZ11-200-ND - IC ADC 11-BIT 200MSPS 56-LFCSP
AD9230-11
Rev. 0 | Page 23 of 28
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Notes/
Comments
ADC Functions
0x08
modes
0
PWDN:
0 = full
(default)
1 =
standby
0
Internal power-down mode:
000 = normal (power-up, default)
001 = full power-down
010 = standby
011 = normal (power-up)
Note: external PWDN pin
overrides this setting
0x00
Determines various
generic modes of
chip operation.
0x09
clock
0
Duty
cycle
stabilizer:
0 =
disabled
1 =
enabled
(default)
0x01
0x0D
test_io
0
Reset
PN23
gen:
1 = on
0 = off
(default)
Reset
PN9 gen:
1 = on
0 = off
(default)
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
0x00
When this register
is set, the test data
is placed on the
output pins in
place of normal
data.
0x0F
ain_config
0
Analog
input
disable:
1 = on
0 = off
(default)
CML
enable:
1 = on
0 = off
(default)
0
0x00
0x14
output_mode
0
Output
enable:
0 =
enable
(default)
1 =
disable
DDR:
1 =
enabled
0 =
disabled
(default)
Output
invert:
1 = on
0 = off
(default)
Data format select:
00 = offset binary
(default)
01 = twos
complement
10 = gray code
0x00
0x15
output_adjust
0
LVDS
course
adjust:
0 =
3.5 mA
(default)
1 =
2.0 mA
LVDS fine adjust:
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
0x00
16
output_phase
Output
clock
polarity
1 =
inverted
0 =
normal
(default)
0
0x03
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