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參數(shù)資料
| 型號： | AD9146-M5375-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 設(shè)計資源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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Data Sheet
AD9146
Rev. A | Page 31 of 56
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 37. When Register 0x16, Bits[2:0] are set to 000, the
sampling point of the data bus nominally occurs 165 ps after
each edge of the DCI signal and has an uncertainty of ±285 ps,
as illustrated by the data valid window shown in Figure 37. The
data and FRAME signals must be valid throughout this window.
The data and FRAME signals may change at any time between
data valid windows.
The setup (tS) and hold (tH) times, with respect to the edges,
are shown in Figure 37. The minimum setup and hold times
are shown in Table 14.
096
91
-042
DCI
DATA
tH
tS
DVW OR
KOW
NOTES
1. DVW = DATA VALID WINDOW. KOW = KEEP OUT WINDOW.
Figure 37. Timing Diagram for Input Data Port
Table 14. Data to DCI Setup and Hold Times
DCI Delay
Register 0x16,
Bits[1:0]
Minimum Setup
Time, tS (ns)
Minimum Hold
Time, tH (ns)
Sampling
Interval (ns)
00
0.12
0.45
0.57
01
0.01
0.74
0.73
10
0.2
1.03
0.83
11
0.28
1.16
0.88
Bypass DCI Delay Mode
An additional option for the timing of the data, DCI, and
FRAME signals requires the DCI to be delayed by 90° ahead
of the data and FRAME signals. In bypass DCI delay mode, the
DCI signal is placed in the optimal data valid window outside
the part, and the delay circuitry inside the part is bypassed. This
mode provides a smaller sampling window that allows for a wider
range of placement area for correct sampling edges. The bypass
DCI delay mode is enabled by setting Bit 2 in Register 0x16 to 1.
The sampling point of the data bus nominally occurs 90 ps before
each edge of the DCI signal and has an uncertainty of ±180 ps,
as illustrated by the sampling interval shown in Figure 38. The
resulting setup and hold times for this mode are as follows:
Minimum setup time (tS): 0.27 ns
Minimum hold time (tH): 0.09 ns
Sampling interval: 0.36 ns
Figure 38 shows the timing for the bypass DCI delay mode.
DCI
DATA
tH
tS
DVW OR
KOW
0
96
91-
099
NOTES
1. DVW = DATA VALID WINDOW. KOW = KEEP OUT WINDOW.
Figure 38. Timing Diagram for Input Data Port (Bypass DCI Delay Mode)
The data interface timing can be verified using the sample error
detection (SED) circuitry. See the Interface Timing Validation
section for more information.
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