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參數(shù)資料
| 型號： | AD9146-M5375-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 設計資源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行 |
| 設置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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AD9146
Data Sheet
Rev. A | Page 20 of 56
Table 11. Device Configuration Register Descriptions
Register
Name
Address
(Hex)
Bits
Name
Description
Default
Comm
0x00
7
SDIO
SDIO pin operation. To enable data readback, set this bit to 1.
0
0 = SDIO operates as an input only.
1 = SDIO operates as a bidirectional input/output.
6
LSB_FIRST
Serial port communication, LSB or MSB first.
0
0 = MSB first.
1 = LSB first.
5
Reset
The device is placed in reset when this bit is written high
and remains in reset until the bit is written low.
0
Power
Control
0x01
7
Power down I DAC
1 = power down I DAC.
0
6
Power down Q DAC
1 = power down Q DAC.
0
5
Power down data
receiver
1 = power down the input data receiver.
0
4
Power down auxiliary
ADC
1 = power down the auxiliary ADC for temperature sensor.
1
3
Power down auxiliary
DACs and reference
1 = power down the auxiliary DACs and the voltage reference.
0
2
Power down clocks
1 = power down the clocks.
0
Tx Enable
Control
0x02
6
Extended delay length
Time delay from when the TXENABLE pin is brought high to
when the DAC begins transmitting data. See the Tx Enable
section for more information.
0 = delay the outputs by 12 to 13 DAC/64 clock edges.
1 = delay the outputs by 19 to 20 DAC/64 clock edges.
0
5
Enable extended delay
The transmit delay, regardless of whether the extended delay
option is selected, has an inherent fixed delay of 10 DAC clock
cycles. When the extended delay is disabled, there is a mini-
mum delay time in the outputs of 1 to 2 DAC/64 clock edges
from when the TXENABLE pin is brought high.
0 = disable the extended delay option. Delays the outputs
by 1 to 2 DAC/64 clock edges.
1 = enable the extended delay option. Delays the outputs
based on the setting of Bit 6.
0
4
Power down voltage
reference
0 = no power-down of the internal voltage reference.
1 = power down the internal voltage reference when the
TXENABLE pin is held low.
0
3
Power down PLL
0 = no power-down of the on-chip PLL.
1 = power down the on-chip PLL when the TXENABLE pin is
held low.
0
2
Power down DACs
0 = no power-down of the DAC cores.
1 = power down the DAC cores when the TXENABLE pin is
held low.
0
1
Power down FIFO
0 = no power-down of the FIFO.
1 = power down the FIFO when the TXENABLE pin is held
low.
0
Power down filters
0 = no power-down of the interpolation filters.
1 = power down the interpolation filters when the
TXENABLE pin is held low.
0
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