參數(shù)資料
型號(hào): AD9146-M5375-EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/56頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9146 DAC
設(shè)計(jì)資源: AD9146-M5375-EBZ Schematic
AD9146-M5375-EBZ Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC+®
DAC 的數(shù)量: 2
位數(shù): 16
采樣率(每秒): 1G
數(shù)據(jù)接口: 串行
設(shè)置時(shí)間: 20ns
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9146
Data Sheet
AD9146
Rev. A | Page 21 of 56
Register
Name
Address
(Hex)
Bits
Name
Description
Default
Data Format
0x03
7
Binary data format
0 = input data is in twos complement format.
0
1 = input data is in binary format.
6
Q data first
Indicates I/Q data pairing on data input.
0
0 = I data sent to data receiver first.
1 = Q data sent to data receiver first.
5
MSB swap
Swaps the bit order of the data input port.
0
0 = order of the data bits corresponds to the pin descriptions.
1 = bit designations are swapped; most significant bits
become the least significant bits.
[1:0]
Data Bus Width[1:0]
Data receiver interface mode. See the LVDS Input Data Ports
section for information about the operation of the different
interface modes.
00
00 = byte mode; 8-bit interface bus width.
01 = byte mode; 8-bit interface bus width.
10 = nibble mode; 4-bit interface bus width.
11 = invalid.
Interrupt
Enable
0x04
7
Enable PLL lock lost
1 = enable interrupt for PLL lock lost.
0
6
Enable PLL locked
1 = enable interrupt for PLL locked.
0
5
Enable sync signal lost
1 = enable interrupt for sync signal lost.
0
4
Enable sync signal locked
1 = enable interrupt for sync signal locked.
0
1
Enable FIFO Warning 1
1 = enable interrupt for FIFO Warning 1.
0
Enable FIFO Warning 2
1 = enable interrupt for FIFO Warning 2.
0
0x05
[7:5]
Set to 0
Set these bits to 0.
000
4
Enable AED compare pass
1 = enable interrupt for AED comparison pass.
0
3
Enable AED compare fail
1 = enable interrupt for AED comparison fail.
0
2
Enable SED compare fail
1 = enable interrupt for SED comparison fail.
0
[1:0]
Set to 0
Set these bits to 0.
00
Event Flag
0x06
7
PLL lock lost
1 = indicates that the PLL, which had been previously
locked, has unlocked from the reference signal. This is a
latched signal.
N/A
6
PLL locked
1 = indicates that the PLL has locked to the reference
clock input.
N/A
5
Sync signal lost
1 = indicates that the sync logic, which had been previously
locked, has lost alignment. This is a latched signal.
N/A
4
Sync signal locked
1 = indicates that the sync logic has achieved sync
alignment. This is indicated when no phase changes
were requested for at least a few full averaging cycles.
N/A
1
FIFO Warning 1
1 = indicates that the difference between the FIFO read
and write pointers is 1.
N/A
0
FIFO Warning 2
1 = indicates that the difference between the FIFO read
and write pointers is 2.
N/A
Note that all event flags are cleared by writing the respective bit high.
0x07
4
AED compare pass
1 = indicates that the SED logic detected a valid input data
pattern compared against the preprogrammed expected
values. This is a latched signal.
N/A
3
AED compare fail
1 = indicates that the SED logic detected an invalid input data
pattern compared against the preprogrammed expected
values. This latched signal is automatically cleared when
eight valid I/Q data pairs are received.
N/A
2
SED compare fail
1 = indicates that the SED logic detected an invalid input
data pattern compared against the preprogrammed
expected values. This is a latched signal.
N/A
Note that all event flags are cleared by writing the respective bit high.
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