參數(shù)資料
型號(hào): AD8465WBCPZ-R7
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 0K
描述: IC COMPARATOR LVDS R-R 12LFCSP
標(biāo)準(zhǔn)包裝: 1,500
類(lèi)型: 帶鎖銷(xiāo)
元件數(shù): 1
輸出類(lèi)型: 補(bǔ)充型,LVDS,滿(mǎn)擺幅
電壓 - 電源,單路/雙路(±): 2.5 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 2mV @ 2.5V
電流 - 輸入偏壓(最小值): 5µA @ 2.5V
電流 - 輸出(標(biāo)準(zhǔn)): 50mA
電流 - 靜態(tài)(最大值): 3mA
CMRR, PSRR(標(biāo)準(zhǔn)): 50dB CMRR,60dB PSRR
傳輸延遲(最大): 3ns
磁滯: 100µV
工作溫度: -40°C ~ 125°C
封裝/外殼: 12-VFQFN 裸露焊盤(pán),CSP
安裝類(lèi)型: 表面貼裝
包裝: 帶卷 (TR)
AD8465
Data Sheet
Rev. A | Page 12 of 16
CROSSOVER BIAS POINTS
The AD8465 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND varies the amount of hysteresis
in a predictable and stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes hysteresis. The maxi-
mum hysteresis that can be applied using this pin is approximately
160 mV. Figure 19 illustrates the amount of hysteresis applied as
a function of external resistor value. Figure 10 illustrates hysteresis
as a function of current.
Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near the
VCCI rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs.
At this point, normally VCCI/2, the direction of the bias current
reverses and there are changes in measured offset voltages and
currents.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or
poor bypassing, oscillation is observed. This oscillation is
due to the high gain bandwidth of the comparator in combina-
tion with feedback parasitics in the package and PCB. In many
applications, chattering is not harmful.
The hysteresis control pin appears as a 1.25 V bias voltage
seen through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the LE/HYS pin because it
would likely degrade the jitter performance of the device and
impair the latch function. As described in the Using/Disabling
the Latch Feature section, hysteresis control need not compro-
mise the latch function.
0
50
100
150
200
250
50
100
150
200
250
300
350
400
450
500
HYSTERESIS RESISTOR (k)
H
Y
ST
E
R
ES
IS
(m
V)
VCC = 2.5V
VCC = 5.5V
07
95
8-
01
9
Figure 19. Hysteresis vs. RHYS Control Resistor
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