參數(shù)資料
型號: AD8465WBCPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 12/16頁
文件大?。?/td> 0K
描述: IC COMPARATOR LVDS R-R 12LFCSP
標(biāo)準(zhǔn)包裝: 1,500
類型: 帶鎖銷
元件數(shù): 1
輸出類型: 補(bǔ)充型,LVDS,滿擺幅
電壓 - 電源,單路/雙路(±): 2.5 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 2mV @ 2.5V
電流 - 輸入偏壓(最小值): 5µA @ 2.5V
電流 - 輸出(標(biāo)準(zhǔn)): 50mA
電流 - 靜態(tài)(最大值): 3mA
CMRR, PSRR(標(biāo)準(zhǔn)): 50dB CMRR,60dB PSRR
傳輸延遲(最大): 3ns
磁滯: 100µV
工作溫度: -40°C ~ 125°C
封裝/外殼: 12-VFQFN 裸露焊盤,CSP
安裝類型: 表面貼裝
包裝: 帶卷 (TR)
Data Sheet
AD8465
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the AD8465 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
VN ± VOS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
tH
tPDL
tPLOH
tF
VIN
VOD
tS
tPL
50%
Q OUTPUT
tPDH
tPLOL
tR
0
79
58
-00
2
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tPDH
Input-to-Output High Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input-to-Output Low Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch Enable-to-Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch Enable-to-Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal high-to-low
transition to the 50% point of an output high-to-low transition.
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum Latch Enable Pulse Width
Minimum time that the latch enable signal must be high to acquire an input signal change.
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
tR
Output Rise Time
Amount of time required to transition from a low-to-high output as measured at the
20% and 80% points.
tF
Output Fall Time
Amount of time required to transition from a high-to-low output as measured at the
20% and 80% points.
VOD
Voltage Overdrive
Difference between the input voltages, VP and VN.
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