參數(shù)資料
型號(hào)： AD8376ACPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 0K
描述： IC AMP VGA DIFF DUAL 32LFCSP
產(chǎn)品培訓(xùn)模塊： Differential Circuit Design Techniques for Communication Applications
設(shè)計(jì)資源： Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
High Performance, Dual Channel IF Sampling Receiver (CN0140)
標(biāo)準(zhǔn)包裝： 1
放大器類(lèi)型： 可變?cè)鲆?br>
電路數(shù)： 2
輸出類(lèi)型： 差分
轉(zhuǎn)換速率： 5000 V/µs
-3db帶寬： 700MHz
電流 - 輸入偏壓： 900nA
電流 - 電源： 250mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
其它名稱： AD8376ACPZ-R7DKR
Data Sheet
AD8376
Rev. B | Page 13 of 24
APPLICATIONS
BASIC CONNECTIONS
Figure 36 shows the basic connections for operating the
AD8376. A voltage between 4.5 V and 5.5 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of
0.1 μF placed as close as possible to the device.
The outputs of the AD8376 are open collectors that need to be
pulled up to the positive supply with 1 H RF chokes. The differ-
ential outputs are biased to the positive supply and require ac-
coupling capacitors, preferably 0.1 F. Similarly, the input pins
are at bias voltages of about 2 V above ground and should be ac-
coupled as well. The ac-coupling capacitors and the RF chokes are
the principle limitations for operation at low frequencies.
To enable each channel of the AD8376, the ENBA or ENBB pin
must be pulled high. Taking ENBA or ENBB low puts the
channels of the AD8376 in sleep mode, reducing current
consumption to approximately 5 mA per channel at ambient.
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
The AD8376 can be configured as a single-ended input to
differential output driver, as shown in Figure 34. A 150 Ω
resistor in parallel with the input impedance of input pin
provides an impedance matching of 50 Ω. The voltage gain and
the bandwidth of this configuration, using a 150 Ω load,
remains the same as when using a differential input.
Using a single-ended input decreases the power gain by 3 dB
and limits distortion cancellation. Consequently, the second-
order distortion is degraded. The third-order distortion remains
low to 200 MHz, as shown in Figure 35.
5
0.1F
37.5
150
1/2
AD8376
1H
150
A0 TO A4
1H
+5V
06725-
035
VCM
0.1F
50
AC
Figure 34. Single-Ended-to-Differential Conversion
Featuring of the AD8376
06725-
036
–60
–65
–70
–75
–80
–85
–90
–95
–100
HARM
O
NI
C
DI
S
T
O
RT
IO
N
(
d
Bc)
0
200
150
100
50
FREQUENCY (MHz)
HD2
HD3
Figure 35. Harmonic Distortion vs. Frequency of
Single-Ended-to-Differential Conversion
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