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| 型號： | AD8376ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP VGA DIFF DUAL 32LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Differential Circuit Design Techniques for Communication Applications |
| 設(shè)計資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 2 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 5000 V/µs |
| -3db帶寬： | 700MHz |
| 電流 - 輸入偏壓： | 900nA |
| 電流 - 電源： | 250mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 其它名稱： | AD8376ACPZ-R7DKR |
AD8376
Data Sheet
Rev. B | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
A2
2
A3
3
A4
4
VCMA
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND.
SOLDER TO A LOW IMPEDANCE GROUND PLANE.
5
VCMB
6
B4
7
B3
8
B2
24 OPA+
23 OPA–
22 ENBA
21 GNDA
20 GNDB
19 ENBB
18 OPB–
17 OPB+
9
B1
10
B0
1
IP
B+
12
IP
B–
13
G
NDB
14
V
CCB
15
O
P
B+
16
OP
B
–
32
A1
31
A0
30
IP
A+
29
IP
A–
28
G
ND
A
27
V
CC
A
26
O
P
A+
25
O
P
A–
AD8376
TOP VIEW
(Not to Scale)
06725-
002
Figure 3. 32-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
A2
MSB 2 for the Gain Control Interface for Channel A.
2
A3
MSB 1 for the Gain Control Interface for Channel A.
3
A4
MSB for the 5-Bit Gain Control Interface for Channel A.
4
VCMA
Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor.
5
VCMB
Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor.
6
B4
MSB for the 5-Bit Gain Control Interface for Channel B.
7
B3
MSB 1 for the Gain Control Interface for Channel B.
8
B2
MSB 2 for the Gain Control Interface for Channel B.
9
B1
LSB + 1 for the Gain Control Interface for Channel B.
10
B0
LSB for the Gain Control Interface for Channel B.
11
IPB+
Channel B Positive Input.
12
IPB
Channel B Negative Input.
13, 20
GNDB
Device Common (DC Ground) for Channel B.
14
VCCB
Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor.
15, 17
OPB+
Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal.
16, 18
OPB
Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal.
19
ENBB
Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low.
21, 28
GNDA
Device Common (DC Ground) for Channel A.
22
ENBA
Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low.
23, 25
OPA
Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal.
24, 26
OPA+
Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal.
27
VCCA
Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor.
29
IPA
Channel A Negative Input.
30
IPA+
Channel A Positive Input.
31
A0
LSB for the Gain Control Interface for Channel A.
32
A1
LSB + 1 for the Gain Control Interface for Channel A.
Exposed Pad
Internally connected to ground. Solder to a low impedance ground plane.
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