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參數(shù)資料
| 型號： | AD8376ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC AMP VGA DIFF DUAL 32LFCSP |
| 產(chǎn)品培訓模塊： | Differential Circuit Design Techniques for Communication Applications |
| 設計資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 標準包裝： | 1 |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 2 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 5000 V/µs |
| -3db帶寬： | 700MHz |
| 電流 - 輸入偏壓： | 900nA |
| 電流 - 電源： | 250mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 其它名稱： | AD8376ACPZ-R7DKR |
AD8376
Data Sheet
Rev. B | Page 18 of 24
LAYOUT CONSIDERATIONS
Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the
board, care should be taken to minimize the parasitic capaci-
tance due to the routing that connects the corresponding
outputs together. A good practice is to avoid any ground or
power plane under this routing region and under the chokes to
minimize the parasitic capacitance.
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8376 was
performed using a dedicated differential input to differential
output characterization board. Figure 45 shows the layout of the
characterization board. The board was designed for optimum
impedance matching into a 75 Ω system. Because both the
input and output impedances of the AD8376 are 150 Ω differ-
entially, 75 Ω impedance runs were used to match 75 Ω network
analyzer port impedances. On-board 1 μH inductors were used
for output biasing, and the output board traces were designed
for minimum capacitance.
0.1F
06725-
050
L1
1H
L2
1H
0.1F
+5V
5
A0 TO A4
AC
75 TRACES
75
AC
1/2
AD8376
Figure 43. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
0.1F
TC3-1T
06725-
051
T1
0.1F
330
25
50
+9V
5
A0 TO A4
50
96
AC
1/2
AD8376
Figure 44. Test Circuit for Time Domain Measurements
06275-
044
Figure 45. Differential-to-Differential Characterization Board
Circuit Side Layout
C1
0.1F
C2
0.1F
TC3-1T
06725-
043
T1
L1
1H
L2
1H
C3
0.1F
C4
0.1F
R1
62
R2
62
R4
25
R3
25
ETC1-1-13
T2
50
PAD LOSS = 11dB
+5V
5
A0 TO A4
50
AC
1/2
AD8376
Figure 46. Test Circuit for Distortion, Gain, and Noise
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