CD RD
參數(shù)資料
型號(hào): AD8352ACPZ-R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 0K
描述: IC AMP RF/IF DIFF 2GHZ 16-LFCSP
產(chǎn)品培訓(xùn)模塊: Differential Circuit Design Techniques for Communication Applications
設(shè)計(jì)資源: Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046)
標(biāo)準(zhǔn)包裝: 1
放大器類型: RF/IF 差分
電路數(shù): 1
輸出類型: 差分
轉(zhuǎn)換速率: 8000 V/µs
-3db帶寬: 2.2GHz
電流 - 輸入偏壓: 75nA
電流 - 電源: 37mA
電壓 - 電源,單路/雙路(±): 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 550 (CN2011-ZH PDF)
其它名稱: AD8352ACPZ-R7DKR
AD8352
Rev. B | Page 15 of 20
0
57
28
-0
12
AD8352
50
0
CD
RD
RG
0.1F
16
1
2
3
4
5
24
0.1F
10
24
0.1F
11
8, 13
14
VCC
AD9445
IF/RF INPUT
ADT1-1WT
FREQUENCY (MHz)
AM
P
L
IT
UD
E
(
d
BF
S
)
0
–150
052.50
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25
05
72
8-
03
5
SNR = 61.98dBc
NOISE FLOOR = –111.2dB
FUND1 = –7.072dBFS
FUND2 = –7.043dBFS
IMD (2F2-F1) = –89dBc
IMD (2F1-F2) = –88dBc
Figure 34. Differential Input to the AD8352 Driving the AD9445
RD RG
25
50
AD8352
CD
33
0.1F
AC
VIP
VIN
VOP
VON
RN
200
AD9445
VIN+
VIN–
057
28-
0
33
Figure 37. Two Tone Distortion AD8352 Driving AD9445,
Encode Clock @ 105 MHz with fC @ 100 MHz (AV = 10 dB),
Analog In = 98 MHz and 101 MHz, See Figure 34
LAYOUT AND TRANSMISSION LINE EFFECTS
High Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies resulting
in excessive gain peaking or possible oscillation. If RF transmission
lines connecting the input or output are used, they should be
designed such that stray capacitance at the input/output pins is
minimized. In many board designs, the signal trace widths should
be minimal where the driver/ receiver is more than one-eighth
of the wavelength from the AD8352. This nontransmission line
configuration requires that underlying and adjacent ground and
low impedance planes be dropped from the signal lines. In a
similar fashion, stray capacitance should be minimized near the
RG, CD, and RD components and associated traces. This also
requires not placing low impedance planes near these components.
Refer to the evaluation board layout (Figure 39 and Figure 40)
for more information. Excessive stray capacitance at these nodes
results in unwanted high frequency distortion. The 0.1 μF supply
decoupling capacitors need to be close to the amplifier. This
includes Signal Capacitor C2 through Signal Capacitor C5.
Figure 35. Single-Ended Input to the AD8352 Driving the AD9445
0
–150
0
52.50
FREQUENCY (MHz)
AM
P
L
IT
UD
E
(
d
BF
S
)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25
SNR = 67.26dBc
SFDR = 83.18dBc
NOISE FLOOR = –110.5dB
FUND = –1.074dBFS
SECOND = –83.14dBc
THIRD = –85.39dBc
05
72
8-
03
4
Figure 36. Single Tone Distortion AD8352 Driving AD9445,
Encode Clock @ 105 MHz with fC @ 100 MHz (AV = 10 dB), See Figure 34
Parasitic suppressing resistors (R5, R6, R7, and R11) can be
used at the device input/output pins. Use 25 Ω series resistors
(Size 0402) to adequately de-Q the input and output system
from most parasitics without a significant decrease in gain. In
general, if proper board layout techniques are used, the suppression
resistors are not necessarily required. Output Parasitic Suppression
Resistor R7 and Output Parasitic Suppression Resistor R11 can
be required for driving some switch capacitor ADCs. These
suppressors, with Input C of the converter (and possibly added
External Shunt C), help provide charge kickback isolation and
improve overall distortion at high encode rates.
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