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參數(shù)資料
| 型號(hào)： | AD8352ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/20頁(yè) |
| 文件大小： | 0K |
| 描述： | IC AMP RF/IF DIFF 2GHZ 16-LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Differential Circuit Design Techniques for Communication Applications |
| 設(shè)計(jì)資源： | Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | RF/IF 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 8000 V/µs |
| -3db帶寬： | 2.2GHz |
| 電流 - 輸入偏壓： | 75nA |
| 電流 - 電源： | 37mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 550 (CN2011-ZH PDF) |
| 其它名稱： | AD8352ACPZ-R7DKR |
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AD8352
Rev. B | Page 3 of 20
SPECIFICATIONS
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless
otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6).
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth
AV = 6 dB, VOUT ≤ 1.0 V p-p
2500
MHz
AV = 10 dB, VOUT ≤ 1.0 V p-p
2200
MHz
AV = 14 dB, VOUT ≤ 1.0 V p-p
1800
MHz
Bandwidth for 0.1 dB Flatness
3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p
190
MHz
Bandwidth for 0.2 dB Flatness
3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p
300
MHz
Gain Accuracy
Using 1% resistor for RG, 0 dB ≤ AV ≤ 20 dB
±1
dB
Gain Supply Sensitivity
VS ± 5%
0.06
dB/V
Gain Temperature Sensitivity
40°C to +85°C
4
mdB/°C
Slew Rate
RL = 1 kΩ, VOUT = 2 V step
9
V/ns
RL = 200 Ω, VOUT = 2 V step
8
V/ns
Settling Time
2 V step to 1%
<2
ns
Overdrive Recovery Time
VIN = 4 V to 0 V step, VOUT ≤ ±10 mV
<3
ns
Reverse Isolation (S12)
80
dB
INPUT/OUTPUT CHARACTERISTICS
Common-Mode Nominal
VCC/2
V
Voltage Adjustment Range
1.2 to 3.8
V
Maximum Output Voltage Swing
1 dB compressed
6
V p-p
Output Common-Mode Offset
Referenced to VCC/2
100
+20
mV
Output Common-Mode Drift
40°C to +85°C
0.25
mV/°C
Output Differential Offset Voltage
20
+20
mV
Common-Mode Rejection Ratio (CMRR)
57
dB
Output Differential Offset Drift
40°C to +85°C
0.15
mV/°C
Input Bias Current
±5
μA
Input Resistance
3
kΩ
Input Capacitance (Single Ended)
0.9
pF
Output Resistance
100
Ω
Output Capacitance
3
pF
POWER INTERFACE
Supply Voltage
3
5
5.5
V
ENB Threshold
1.5
V
ENB Input Bias Current
ENB at 3 V
75
nA
ENB at 0.6 V
125
μA
Quiescent Current
ENB at 3 V
35
37
39
mA
ENB at 0.6 V
5.3
mA
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