- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1893 > AD8303ARZ-REEL (Analog Devices Inc)IC DAC 12BIT SERIAL 14SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD8303ARZ-REEL |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SERIAL 14SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD8303 Obsolescence 15/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 14µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 9.6mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類(lèi)型： | * |
| 采樣率（每秒）： | * |
| 其它名稱(chēng)： | AD8303ARZ-REELDKR |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
AD8303
REV. 0
–11–
SHUTDOWN (SHDN)
The shutdown feature is activated when SHDN is pulled low.
While the AD8303 is in shutdown mode, the voltage reference,
DACs, and output amplifiers are all turned off. Supply current
is less than 1
A. The DAC output voltage goes to 0 V, pulled
to GND by the 12.5 k
feedback resistors (Figure 22).
If power (i.e., VDD) is maintained to the AD8303 during
shutdown, the value stored in the DAC input latches will not
change. When the SHDN pin is driven high, the DACs will
return to the same voltages as before shutdown. The CMOS
logic section of the AD8303 remains active while SHDN is low.
Thus, new data can be loaded while the DACs are shut down
and, when SHDN goes high, the DACs will assume the new
output voltage. The AD8303 recovers from shutdown very
quickly. The voltage output settling time after shutdown is
typically only a few microseconds longer than the normal
settling time (Figure 20).
SDI
CLK
CS
LDA
LDB
RS
MSB
SHDN
AD8303
13
2, 14
14
4
1
VOUTA
VOUTB
+3V TO +5V
AGND DGND
VDD
500pF
2k
7
6
5
8
10
9
11
12
0.1F
10F
0V
≤ V
OUT ≤ 2.0475V
VOUTA, VOUTB
Figure 29. Unipolar Output Operation
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD8303. As shown
in Figure 29, the AD8303 has been designed to drive loads as
low as 2 k
in parallel with 500 pF. The code table for this
operation is shown in Table II.
Table II. Unipolar Code Table
Hexadecimal Number Decimal Number
Analog Output
in DAC Register
Voltage (V)
FFF
4095
2.0475
801
2049
1.0245
800
2048
1.024
7FF
2047
1.0235
000
0
GENERATING “BIPOLAR” OUTPUTS WITH A SINGLE
SUPPLY
To maximize output signal swings in single supply operation,
many circuit designs employ a “false-ground” configuration.
This method defines a voltage, usually at one half of full scale or
at one half of the power supply, as the “ground” reference.
Signals are then measured differentially from the false ground,
which produces a “quasi-bipolar” output swing.
The AD8303’s voltage reference output, combined with an op
amp, can provide a temperature compensated false-ground
reference, as shown in Figure 30. The op amp amplifies the
AD8303’s 1.0 V reference by 1.024 to provide an analog
common (false ground) at one-half scale (1.024 V). With this
method, the DAC output is
±1.024 V (referenced to the false
ground). The “Quasi-Bipolar” code table is given in Table III.
4
1
AD8303
13
2
3
VOUTA
VREF
+3V
AGND DGND
VDD
+3V
OP193
VOUT = ±1.024V
(REFERENCED TO
SIGNAL GROUND)
R2A
97.6k
1F
0.022F
R1
2.4k
SIGNAL GROUND
(FALSE GROUND, +1.024V)
100
R2B*
2k
*ZERO-SCALE TRIM
Figure 30. A False-Ground Generator
Table III. Quasi-Bipolar Code Table
DAC
Analog
Hexadecimal
Decimal
Output Common
“Bipolar”
Number
Number In
Voltage (False-Ground) Analog
in DAC Register DAC Register (V)
Voltage (V)
FFF
4095
2.0475
1.024
+1.2035
801
2049
1.0245
1.024
0.0005
800
2048
1.024
0
7FF
2047
1.0235
1.024
–0.0005
000
0
1.024
–1.024
Since the AD8303’s reference voltage output limits are typical, a
trim potentiometer is included so that the “false-ground” output
can be adjusted to exactly 1.024 V. To maintain accuracy,
resistors R1 and R2A must be of the same type (preferably
metal film) to insure temperature coefficient matching. The
circuit includes compensation to allow for a 1
F bypass
capacitor at the false-ground output. The benefit of a large
capacitor is that not only does the false ground present a very
low dc resistance to the load, but its ac impedance is low as
well.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8391AR-REEL7 | IC XDSL LINE DVR W/PWR DN 8-SOIC |
| AD8392AAREZ | IC ADSL/ADSL2 LINE DRVR 28-TSSOP |
| AD8394AREZ-R7 | IC OPAMP ADSL/ADSL2 DL 20TSSOP |
| AD8396ACPZ-RL | IC LINE DRVR ADSL/ADSL2 16LFCSP |
| AD8398ACPZ-R7 | IC LINE DRVR DUAL VDSL 16-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8303JRU | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 14-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:IC,DUAL 12BIT,+3V,COMPLETE DAC - Bulk |
| AD8303JRU-REEL | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 14-Pin TSSOP T/R |
| AD8303JRUZ | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 14-Pin TSSOP |
| AD8304 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:160 dB Range (100 pA -10 mA) Logarithmic Converter |
| AD8304ARU | 功能描述:IC LOGARITHM CONV 160DB 14-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 放大器 - 專(zhuān)用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類(lèi)型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類(lèi)型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤(pán) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。