V
參數(shù)資料
型號(hào): AD8303ARZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT SERIAL 14SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD8303 Obsolescence 15/Apr/2011
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 14µs
位數(shù): 12
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 9.6mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOICN
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: *
采樣率(每秒): *
其它名稱: AD8303ARZ-REELDKR
AD8303–Typical Performance Characteristics
REV. 0
–6–
120
40
02
1
–80
0
80
–120
–40
OUTPUT VOLTAGE – Volts
OUTPUT
CURRENT
mA
VDD = +5V
POSITIVE
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
DATA = 800H
RL TIED TO
+1.024V
Figure 4. I
OUT vs. VOUT
75
0
60
45
30
15
10
100
1M
10k
100k
1k
FREQUENCY – Hz
POWER
SUPPLY
REJECTION
dB
TA = +25°C
DATA = 800H
VDD = +3V ± 10%
VDD = +5V ± 10%
Figure 7. Power Supply Rejection
vs. Frequency
100
90
10
0%
10mV
1s
2V
VOUT
CLK
Figure 10. Clock Feedthrough vs.
Time
7
6
0
01
5
34
3
5
4
2
LOGIC VOLTAGE – Volts
SUPPLY
CURRENT
mA
VDD = +5V
VDD = +3V
TA = +25°C
DATA = 000H
2
1
Figure 6. Supply Current vs. Logic
Input Voltage
100
90
10
0%
1V
5s
5V
VOUT
LD
Figure 9. Large Signal Settling Time
2.5
2.0
–0.5
1.5
1.0
0.5
0
–55 –35
125
5
25
45
65
85 105
–15
V
OUT
DRIFT
mV
TEMPERATURE –
°C
VDD = +2.7V
VDD = +5.5V
NO LOAD
SS = 200 UNITS
NORMALIZED TO +25
°C
Figure 12. Full-Scale Voltage Drift
vs. Temperature
TIME = 100s/DIV
BROADBAND
NOISE
200V/DIV
100
90
10
0%
TA = +25°C
NBW = 635kHz
Figure 5. Broadband Noise
CODE 800H TO 7FFH
100
90
10
0%
50mV
200ns
5V
VOUT
LD
Figure 8. Midscale Transition
Performance
120
100
0
20
60
80
40
–5 –3
1
5
–1
9
TOTAL UNADJUSTED ERROR – LSB
FREQUENCY
TUE =
∑ (INL+ZS+FS)
SS = 200 UNITS
VDD = +2.7V
3
7
11 13 15
Figure 11. Total Unadjusted
Error Histogram
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